资源列表
sbq
- 基于fpga和传统示波器工作方式的vhdl程序，通过ad0809采样信号（可兼容tlc5510）再经由8位da转换输出，同时输出外触发锯齿波，建议使用感性小的示波器探头，否则锯齿波低频时会出现失真-Fpga-based and traditional ways of working oscilloscope vhdl procedures, through ad0809 sampling signal (compatible tlc5510) and then through eight da
ddsp
- DDSVHDL程序一测试可以实现-DDS u8BA4 u779 u4994 u4992 u4B09 u8B0 U5B57 u2002 u5C3D u9CF u4E0 u8BA1 u8BA1 u7Ag9 u653
BASE-PAPER
- this files contains base papers for vlsi
rom
- uart 通用异步收发传输器 接收模块和发送模块 附带了常用的波形 三角波 和正弦波-uart universal asynchronous receiver transmitter receiver module and transmitter modules come with a common triangular wave and sine wave
sp6ex14
- verilog,ISE工程。倒车雷达实例，每100ms产生1个超声波测距模块所需的10us高脉冲激励，并用数码管以16进制数据显示经过滤波处理的回响信号的高脉冲计数值（以10us为单位），与此同时，蜂鸣器根据障碍物远近，也会相应的发出不同频率的响声。-verilog, ISE project. Reversing radar instance, every 100ms high pulse generating 10us required an ultrasonic ranging module
clock_finish
- 基于quartus2的数字时钟，时间可调-Based quartus2 digital clock, time is adjustable. . . . .
DDS30k
- 在quartus开发平台基于直接数字频率合成技术利用Verilog语言实现正弦信号和三角波信号发生(Verilog was used to generate sine and triangle wave signals based on direct digital frequency synthesis in quartus development platform.)
fpga3
- 关于FPGA的相关介绍与一些例程代码实现3(About FPGA related introduction and some routine code implementation)
ML_506_3_lcd_1602
- lcd1602的四线控制的verilog源码，在ML506平台上已经通过验证-The lcd1602 four-line control of Verilog source code which has been verified on the ML506 platform.
mp3_player
- 用vhdl结合sopc编写的MP3的程序 可以在硬件上跑通 包含仿真程序-Written in conjunction with vhdl MP3 sopc program can run on the hardware via emulation program included
A4_Vote4
- 一个基于FPGA的四人投票计票程序，程序语言使用Verilog，初学者适用-A FPGA based voting procedure for four people voting
mp3play
- 基于FPGA设计的MP3播放器。可播放SD卡上存储的MP3音频界面。并且在TFT上显示-failed to translate