资源列表
VGA_Controller
- 控制视频在VGA端口输出，包括对其中场信号和消隐信号的控制，对初学者有很大帮助。-output video from VGA port easily！
Synchronis_Bascule_D
- a synchronise bascule in Vhdl
38
- 3-8译码器的vhdl源程序，设置了3个输入端s1,s2,s3-3-8 decoder vhdl source code
crc16
- CRC 16 endcoder/ decoder. The source includes two modules. The first operates with 16 bit register. The second one operates with serial data.
verilog实现串并转换
- verilog实现串并转换的源代码
state_machine
- State Machine for VHDL
spreadspectrum1
- these are verilog files but i am uploading in text(notepad) format
vhdlcodes1
- vhdl programs for 4 bit ripple carry adder in structural and behavioural modelling
Multiplier-code-with-testbench
- VHDL code for synthesizable Multiplier with testbench
serial
- 此为Verilog写的功能测试函数，主要用于模块的测试，本程序已调试成功。-This is the function of test functions written in Verilog, mainly used in the test module, the program has been successful debugging.
vivado2016.2-license
- Vivado Design Suite v2016.2版本license-the license of Vivado Design Suite v2016.2
VHDL写的控制步进电机24byj48的小程序
- VHDL写的控制步进电机24byj48的小程序.验证可用.不过还有待改进