资源列表
xilinx_DDR3_design_guide
- 关于FPGA的DDR3的设计和应用指导，是个很不错的文档，适应学习FPGA的人进行学习研究-FPGA DDR3 design and application guide
car-VHDl
- 计程车计程器，FPGA实现，用VHDL实现，包括LCD12864驱动程序-Taxi taximeter, FPGA implementation, using VHDL realization, including LCD12864 driver
Two_Level_SVPWM
- 代码为两电平SVPWM调制算法的Verilog程序。包括扇区划分、时间计算、死区控制等。(The code is the Verilog program of the two level SVPWM algorithm. It includes sector division, vecter calculation, dead zone control and so on.)
DE2_115_WEB_SERVER_MII_ENET0
- Simple HTTP server using sockets interface of NicheStack TCP/IP and NIOS II SCPU to serve HTML, JPEG, GIF PNG, JS, CSS, SWF, content using RGMII on DE2-115 board
uart_fpga1110
- 自己实现了一个简易的无校验UART协议。altera EP4C6E验证-Own implements a simple no parity UART protocol. altera EP4C6E verification
Top_SD
- 基于FPGA的SD卡驱动程序，简单的读写模块-FPGA-based SD card driver
AutoESL
- 基于ZYNQ-7000EPP开发板的AutoESL 工程，可直接运行在ISE14.4环境下。-Based ZYNQ-7000EPP development board AutoESL project can be run directly in ISE14.4 environment.
DDS
- DDS函数信号发生器，这是我在xilinx平台上实现的，可以产生不同频率，不同函数形式的函数信号。如三角波，方波等-DDS function generator, this is my on xilinx platform, can produce the function of different frequency signals.
ddr_100Mhz_2011.03.12
- 这个工程是用xilinx的MIG生成的对于spartan 3E的实验板的ddr的控制器，我已经能够在上面修改之后加入自己的思想，包括两个dcm的模块。-This project is the MIG generated by xilinx spartan 3E development board for the ddr controller, I have been able to modify the above by adding his own ideas, including the t
HanoiTower
- 使用Verilog HDL 以及VHDL语言，运用FPGA中的VGA显示原理以及键盘控制原理，开发汉诺塔简易游戏(The use of Verilog HDL and VHDL language, the use of FPGA in the VGA display principle and keyboard control principle, the development of Hanoi simple game)
milian
- 源自米联平台开发板的为文档及教程，内部含有部分关键代码，可复制粘贴。(Documentation and tutorials from milian platform development board)
Signal-Processing
- 这是一本信号处理的英文经典教程。相对国内的信号处理教程来说，讲的更为具体易于理解，如果你学习信号处理时感到很抽象的话，这本书对你很有帮助-This is an English classic signal processing tutorial. Are very abstract when compared to the signal processing tutorial, talking about the more specific is easy to understand, if y