资源列表
Quartus
- 1.七段数码管译码器 2.4人表决器 3.4进制加减法计数器~具有进位和借位功能-1. Seven-Segment LED Decoder 2.4 M 3.4 people voting machine counters ~ with addition and subtraction and by-bit binary function
rombcdto7
- rom implementing bcdtosevenseg
rs232top
- 链接 rcv 和txm的测试模块 验证 接受 和 传输模块功能-Links rcv and txm test module validation capabilities to receive and transmit modules
sqrt_vhdl
- This source are usefull function in VHDL You Can finf squar Root solution
dwedew
- pong impmentation on spartan 3e
LEDdecoder
- 基于vhdl的Led七段数码显示的设计。-Led the team respectively VHDL-based digital display design.
ad_conv
- 利用CPLD来控制AD进行电压采样，并将采样值输出-CPLD to control the use of AD to voltage sampling, and sampling the value of output
motor_control
- 步进电机控制程序，用vhdl实现。可实现电机的正反转控制-Stepper motor control program, using vhdl implementation. Positive inversion of motor control can be realized
baud_gen
- Uart是一种通用串行数据总线，用于异步通信。该总线双向通信，可以实现全双工传输和接收。在嵌入式设计中。其中本代码为UART的波特率产生代码。-Uart is a universal serial data bus, used for asynchronous communication. The bus bidirectional communication, can realize the full duplex transmission and reception. In embedded
freq_div2
- 采用VHDL语言设计的分频器，仿真和实际电路板都测试过，没问题。-Divider using VHDL design, simulation and actual circuit boards are tested, no problem.
counter_vhd
- Counter is used to count the value of the memory register in the digital circuits-Counter is used to count the value of the memory register in the digital circuits....
pulse
- 一个产生可调频率和可调占空比Verilog源代码，希望对你起到作用-A variable frequency and variable duty cycle generates Verilog source code, you want to play a role