资源列表
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- 毕业设计中的12层电梯信号的控制程序VHDL-Graduation Design 12-storey elevator signal control procedures VHDL
shifter.rar
- verilog实现的“并行输入、并行输出移位寄存器”,verilog to achieve a " parallel input, parallel output shift register"
counterjia23
- 一个最基础的23进制加法计数器，学习VHDL一定会遇到的。-One of the most 23 hexadecimal adder based counters, learn VHDL will be encountered.
kongtiaokongzhi
- 用状态机方式编写的简单的空调控制器，根据外界不同的温度控制制冷升温-With the state machine approach to the preparation of a simple air-conditioning controller, according to outside temperature of different refrigerant temperature control
mlt
- 基于FPGA 的乘法器 时间两个数相乘，并在数码管显示-Based on the FPGA multiplier time multiplied by the number two, and in digital tube display
1111-Sequence-Detection
- 1111序列检测的设计VHDL代码，用状态机实现111序列检测的设计，如果检测到正确的序列，则led灯亮起，否则熄灭-1111 Sequence Detection design VHDL code, using the state machine to achieve 111 Sequence Detection design, if it detects the correct sequence, led lights, otherwise extinguished
MCUBUS
- 实现MCU与单片机的通信借口 特别强调了对三态门的VHDL编程-MCU VHDL
sipo_reg5
- VHDL语言描述具有同步清零的5位串行输入并行输出移位寄存器代码-VHDL language to describe the clearing of 5 with synchronous serial input parallel output shift register code
ads831
- ADS831模数转换驱动，使用verilog语言写的。-ADS831 analog-digital conversion drive, write verilog language.
clkdiv
- Verilog UART分频时钟 产生9600波特率-Verilog UART baud rate divided clock generated 9600
MS_TMR
- 三模冗余设计，当某一位数据错误时，可以自动进行纠正-Three modular redundancy design, when a data error, can be automatically corrected