资源列表
VHDL
- 用VHDL语言设计七段显示译码器用VHDL语言设计七段显示译码器-VHDL language design with seven-segment display decoder
VHDL
- 实现异步清零和同步时钟功能的十进制加法计数器-Asynchronous and synchronous clock features clear decimal addition Counter
sram
- SRAM的VHDL设计，设计了一个具有4位地址线，8位数据线的SRAM，读写功能独立-SRAM VHDL design, the design of a 4-bit address lines, 8 data lines of SRAM, read and write functions independent
Debounced-program-FPGA
- FPGA消抖程序，用于按键消抖，可作为一个process写入程序-FPGA debounce program for key debounce, the program can be written as a process
eda2
- 7段显示译码器的输入为：IN0…IN3共5根， 7段译码器的逻辑表同学自行设计，要求实现功能为：输入“ 0…15 ”（二进制），输出“ 0…9…F ”（显示数码），输出结果应在数码管（共阴）上显示出来。-failed to translate
BusDelay
- buffer delay vhdl model
xj2
- 基于FPGA，利用VHDL语言对小车循迹进行设计。-Car tracking
random1
- Random binary sequence generator using four flip-flops. It does not require any external input except clock.
pso-vhdl6
- i want verilogHDL and VHDL source coding.please help me-i want verilogHDL and VHDL source coding.please help me.....
state_machin_VHDL
- Introducing BB FlashBack BB FlashBack is a screen recorder - it makes movies of what you see on your PC screen.
sign_det
- 此程序为符号检测的VHDL程序，用于检测输入数据的最高位符号。-This program is a symbol detection VHDL program for detecting the most significant bit of input data symbols.
SRAM.v
- Verilog design of SRAM