资源列表
ptos
- 八位并行数据转换为串行数据依时钟信号串行输出(Eight bit parallel data to serial data)
FPGA-Prototyping-By-Verilog-Examples
- 通过Verilog例子了解FPGA原型设计（书和源码）-FPGA Prototyping By Verilog Examples
FPGA-Prototyping-By-Verilog-Examples
- <FPGA Prototyping By Verilog Examples>是Verilog指导性的书籍，这个压缩文件包含了PDF格式的电子书和书中的源代码，对于您的学习会有很大帮助。-<FPGA Prototyping By Verilog Examples> Verilog guidance books, The compressed file contains a PDF format e-books and the book' s source code,
noise-cancellation
- 脉冲噪声消除 对输入数据循环累加并求平局比较-noise cancellation source code
FPGA 做的音频信号分析仪
- 使用 Xilinx 的 FPGA 做的音频信号分析仪,附详细说明及 VHDL 源程序.
SharpSharpSharpodd_divide_frequency
- 该语言的功能是实现奇数分频，以7分频为例~希望对需要者有用~-The language function is odd division, divided to hope useful for those who need to
lab6
- 在赛灵思的Spartan-3E开发板上做的跑马灯项目，用switch开关控制跑马灯类型-Marquee project in Xilinx Spartan-3E development board to do the switch switch control Marquee type
SCHK
- 10位序列检测器，有序列产生，分频器，按键消抖，序列检测，数码管扫描等几个模块构成，设计天津工业大学课程设计-10 sequence detector with sequence generation, dividers, key debounce, sequence detection, digital scanning, and several other modules, curriculum design, Tianjin Polytechnic University
mul8
- 用verilog设计了一个两个8位二进制数的乘法器(A multiplier of two 8 bit binary numbers is designed with Verilog)
vote
- 设计一个100人投票器，超过70人算通过，用verilog语言设计(Design a 100 person voter, more than 70 people passed, using Verilog language design)
SoCKIT_Materials_14.0
- SocKit FPGA with ARM core -SocKit FPGA with ARM core
用vhdl写实用96例子
- 用vhdl写实用96例子, 有RAM，PID 等(Using VHDL to write practical examples of 96, there are RAM, PID and so on)