资源列表
CCD_drive
- TCD1304 CCD 驱动 AD转 USB2.0传输(This code based on verilog language, worked on EP1C3T144 FPGA chip, developed on Quartus II 12.0 . The ccd's data transformed by USB2.0 after amplified and AD confromed.)
uart
- FPGA的串口通信 v 文件，直接编译就可以串口通信了，波特率9600(FPGA serial communication, V file)
divide
- 使用Verilog硬件描述语言编写的分频功能，语言代码简短明了(Frequency division function)
ass
- FPGA sine wave, 让DE1学生版输出模拟信号。(analog ouput by DE1 developing board)
isjtc
- Use serial programming examples matlab GUI implementation, Independent component analysis for image processing, Realize image watermarking, de-noising, plus noise and other functions.
kdw_tsohcnt
- cctv otu top source source block
OTU_RXBLK
- cctv otu rx block source
OTU_SOHMUX
- cctv otu soh mux source
jt136
- Filtering summation way broadband beamforming, Power System Transient Stability Program, can be transient stability, Monte Carlo simulation method of calculating the American option price and basic descr iption.
eiush
- Based on multi-document image obtained combining technique, Consider shadow rain attenuation and multipath effects Rapid expansion of random spanning tree algorithm.
Vivado Reference Design R1
- vivado FPGA verilog VHDL
asyn_fifo_204b_28
- 通用性异步fifo,性能非常好，推荐给大家(unverisal asyn fifo)