资源列表
DAC
- 这是一段基于FPGA的dac转换代码。欢迎大家下载测试使用。(This is a section of FPGA based DAC conversion code. Welcome to download, test, use.)
FIFO_1
- 利用FIFO模块实现不同时钟模块间的传输(The transmission between different clock modules is realized by using FIFO module)
LSFR
- 线性反馈移位寄存器通常用于实现数据压缩电路中的基于循环冗余码校验的特征分析，应用于需要用伪随机二进制数的应用中。基于vivado的程序设计(Linear feedback shift registers are usually used to perform signature analysis based on cyclic redundancy check in data compression circuits, and are applied to applications requir
ADC
- vhdl analog digital converter
SourceCode
- 生成非标视频行场同步信号及锯齿波驱动电机(Generating non-standard video line field synchronous signal and sawtooth wave drive motor)
fenpin51
- 任意整数分频器，输出方波可调占空比（已仿真下板子验证）第一个系数为分频系数，第二个为高电平所占整个方波的比例(Arbitrary integer frequency divider, output square wave adjustable duty cycle (has been simulated under board verification), the first factor for the frequency division coefficient, the second fo
dengjingdu
- 等精度测量，频率越高精度越高，每一秒取一次数，然后经过乘除法实现，FPGA功能前更大的。还用到STM32 SPI通信(The accuracy of measurement, the higher the frequency accuracy is high, every second to take a number, then after multiplication and division, FPGA function more. STM32 SPI communications are
20170808_fifo_xc5v_v1.5
- FPGA通过fifo进行数据的载入载出，实现数据的暂时存储和传递(FPGA through fifo data loading and unloading, to achieve temporary storage and delivery of data)
jiaotongdeng
- 基于VHDL状态机的交通灯设计（已仿真下载实验板测试）(Traffic light design based on VHDL state machine (simulation download, experimental board test))
结题报告-基于链家网数据的上海二手房房价分析
- 用FPGA 编写的双端口的RAM，可以实现读写，希望通过这个平台与各个大神交流，希望得到大神的批评指正。(Prepared by FPGA double port RAM, you can read and write, and I hope that through this platform to communicate with the great gods, hoping to get criticism of the great god.)
ram_2
- 双端口RAM，可读，可写，用Verilog编写。希望与大神交流，求大神指正。(Dual port RAM, readable and writable, written in Verilog. Hope to communicate with great God, ask God to correct me)
Verilog-数字频率计
- verilog数字频率计设计,内容挺详细(Verilog Frequence Measure)