资源列表
A4_Clock_Top
- 24小时制数字时钟，可自行调节时间，能暂停。(24 hours digital clock, can adjust time, can pause.)
32位CPU IVERILOG源码
- 介绍在FPGA中如何实现32位CPU涉及到额 IVERILOG源码(Describes how to implement 32 bit CPU in FPGA, involving the amount of IVERILOG source code)
verilog_IEEE官方标准手册-2005_IEEE_P1364
- verilog_IEEE官方标准手册，内部有详细的介绍。(Verilog_IEEE official standard manual, the internal details.)
编译xilinx 库步骤
- 关于编译xilinx 软件库的详细步骤，很有帮助。(Compile the steps for the Xilinx Library)
ex_DDS
- 基于Verilog语言实现DDS（数字频率合成器）的设计，有完整的工程设计代码和仿真脚本(Verilog language based on DDS (digital frequency synthesizer) design, there is a complete engineering design code and simulation scr ipts)
fft fpga
- please copy this file very very good source code!!!!
LCD12864程序模块
- 向单片机里输入上述程序，实现驱动LCD的功能(Singlechip input to the above procedures, to achieve the driving function of LCD)
ac_acquire
- ads127l01串联模式，串联了两个芯片，此时最大采样率不能用。osr的值为 01，10，11.(Ads127l01 series mode, in series with two chips, at this time the maximum sampling rate can not be used. The value of OSR is 01, 10, 11.)
基于FPGA的等精度频率计的设计
- 基于FPGA的频率计，采用的方法为等精度。(Frequency meter based on FPGA)
labassin1
- assignment in verilog 3
计算器3
- 基于51单片机 4*4矩阵 实现简单加减乘除，(The realization of a simple add, subtract, multiply and divide)
Xilinx-FPGA-PCIE-Linux驱动程序
- Xilinx-FPGA-PCIE-Linux驱动程序.rar(Xilinx-FPGA-PCIE-Linux.rar)