资源列表
SPtransform
- Verilog HDL编写的串并转换。采用iout类型口。包含源文件和测试文件。用Modsim编译。-Verilog HDL Series and the preparation of the conversion. I used iout types. Includes source and test papers. Modsim compiler used.
news5f
- Verilog HDL语言编写的5分频电路。采用两路时钟相逻辑作用产生。-Verilog HDL prepared by the five-frequency circuits. Clock using two phase logic role.
Uart_TR
- Verilog编写的简单异步串口 完全原创，站长请查看内容-Verilog prepared by the simple asynchronous serial completely original, the station can be accessed content
counter1
- vhdl 计数器源程序，大家看看吧 vhdl 计数器源程序，大家看看吧-vhdl counter source, we see it vhdl counter source, we see it
tenbench
- 硬件描述语言,verilog HDL,实现了解码器的设计-hardware descr iption language, verilog HDL, the decoding of Design
keydisplay
- 全部通过，是我的精心设计，完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.
counter99
- 全部通过，是我的精心设计，完全满足初学者的要求。0-99自动记数-all passed, I was carefully designed, fully meet the requirements of beginners. 0-99 automatic counting
shopdesigned
- 全部通过，是我的精心设计，完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.
pinliji
- 全部通过，是我的精心设计，完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.
FPGAJPEGCODING
- motionjpeg的FPGA编码实现，有点老了，但是可以参考．有些东西和h.264是差不多的．-motionjpeg FPGA Coding, a bit old, but the reference. Some things and h.264 is roughly the same.
arith_lib_standard
- 这是很全的标准库啊，不是1164.vhd，都是一些加，乘，除，平方等操作的包来的．-This is the standard for the whole ah, not 1164.vhd are some increases, multiplication, addition, operational square packages to come.
arith_lib_cadence
- Cadence的VHDL运算库包，实现求方根，平方你是不是以前不知道怎么弄．哈哈．-Cadence VHDL Operational the package, seeking to achieve root, You are not square did not know how get. Ha ha.