资源列表
Verilog_traffic
- Verilog 的交通灯的例子。源代码中有详细的注释。-Verilog traffic lights examples. The source code for detailed comments.
ModelSim_SE_6.1bkey
- ModelSim SE 6.1 (电子仿真)具体破解-ModelSim SE 6.1 (electronic simulation) Specific crack
EPP
- 并口的EPP协议,与外部的FIFO的empty,full信号共同控制数据传输-of EPP parallel port agreement with the external FIFO empty, full common control signal data transmission
20051113104111170
- FPGA的VHDL设计经验总结《小型微型计算机系统》2003年7月-FPGA VHDL design experience, "small micro-computer system," July 2003
20051113130721803
- USB-BLASTER原理图,用于Altera可编程芯片的下载-USB-BLASTER schematics, Altera programmable chips for download
COUNT_100
- 使用Vhdl语言编写的FPGA应用程序,实现的内容是100进制计数器-use Vhdl language FPGA applications, realizing the contents of the 100 NUMBER
等精度频率计
- 使用vhdl语言写的fpga的应用程序,使献策内容为等精度频率计-use of the VHDL language they simply write the application procedures so that such ideas as to accuracy Cymometer
crc_verilog_xilinx
- CRC校验码,用于对数据流进行crc校验。 主要有CRC_16,CRC_8,CRC_32校验。 所用语言为Verilog HDL.-CRC code for the data flow crc check. Main CRC_16, CRC_8, CRC_32 check. The language used for Verilog HDL.
FIRvhdl
- 用vhdl实现一个fir滤波器 设计要求: 1.最小阻带衰减-30db。 2.带内波动小于1db. 3.用MATLIB与MAXPLUS2联合设计与仿真-use VHDL to achieve a fir filter design requirements : 1. The smallest stop band attenuation - 30dB. 2. With fluctuating within less than 1DB. 3. With MATLIB with MAX
指令译码电路的设计
- 指令译码电路的设计。 主要用在数字电路的设计中。 所用语言为Verilog HDL.-instruction decoder circuit design. Mainly used in digital circuit design. The language used for Verilog HDL.
用一位全加器组成四位全加器
- 用一位全加器组成四位全加器. 所用语言是Verilog HDL. 主要用在加法器的设计中。-All-Canadian with a composed four-adder. The language used is the Verilog HDL. In addition main The design.
D触发器的设计
- D触发器的设计 主要用在时序电路中。 所用语言为Verilog HDL.-D flip-flop with the main design of the timing circuit. The language used for Verilog HDL.