资源列表
EDK_timer_ex
- EDK_timer_ex定时器计数器的开发 -EDK_timer_ex timer counter Development
Verilog-statemachine
- 利用Verilog编程实现状态机的例子。很不错的。-use Verilog Programming state machine example. Very good.
cal_verilog
- 计算器芯片的verilog实现代码！ 时序仿真成功-calculator chips to achieve the Verilog code! Timing simulation success
time_clock
- 实用闹钟的verilog代码。不是vhdl的！经过ldv验证-practical alarm the Verilog code. VHDL is not! After certification ldv
SDRAM_C
- SDRAM控制核，已经经过测试，完全可以稍加修改后应用-SDRAM control nuclear, has been tested, we can use a slightly modified
mt48lc2m32b2
- SDRAM控制核，已经经过测试，完全可以稍加修改后应用-SDRAM control nuclear, has been tested, we can use a slightly modified
primetime
- 这是ＶＨＤＬ语言编写的延时测试程序，用来测定ＣＰＬＤ的性能指标-This is the VHDL language delay the test procedure used to determine the performance CPLD
RAMINCREASE
- 这是利用ＣＰＬＤ做ＤＳＰ的存储器扩展的源文件。-CPLD This is done using the DSP memory expansion of the source document.
CPLD_DMA
- 这是一款USB接口ISP1582器件实现DMA传输的辅助电路的硬件设计源代码-This is a ISP1582 USB device DMA transmission of the auxiliary circuit hardware design source code
Evita_VHDL
- VHDL 的非常好用易懂的教学软件。大家试试看。-VHDL very handy and easy to teaching software. We try.
Evita_Verilog
- Verilog 的非常好用易懂的教学软件。-Verilog very handy and easy to teaching software.
[eda]vhdl
- 福州大学EDA选修课所有实验课程代码。VHDL语言描述（vhd），以及电路图（gdf）-Fuzhou University EDA optional courses in all experimental code. VHDL descr iption (vhd), and circuit (GdF)