资源列表
msttr
- msttr是用vhdl语言开发的一个交通灯程序-msttr VHDL language is a development of the traffic lights procedures
路口交通灯
- 个人硬件课程设计,简单实现了FPGA平台的路口交通灯管理,开发环境为MAX+plus-individual hardware curriculum design, a simple realization FPGA platform junction traffic lights management, development environment for MAX plus
sorce
- 一个很好的利用verilog编程实现的cpu程序,一定要好好利用。-a good use of the Verilog Programming cpu procedures, we must make good use of.
alu_vlog
- 学习使用HDL Bencher生成测试积累,并直接调用ModelSim进行仿真的方法.-learning HDL Bencher generate test accumulation, and called directly ModelSim simulation methods.
cpu16
- 一个16位cpu的vhdl代码。具体内容我也不清楚,自己慢慢研究吧-a 16 cpu of VHDL code. Specific content is not clear to me that their study it slowly
SCAN_COUNT
- 用VHDL编写的关于SCAN的一个小程序,希望大家看了后能喜欢,也可以学学哟!-VHDL SCAN prepared on a small procedures in the hope that after reading them you will like and can learn yo!
air_conditioner
- 空调温控电路有限状态自动机, 有TEMP_HIGH和TEMP_LOW 分别与传感器相连用语检测室内温度.-air-conditioning temperature control circuit finite state automaton, and TEMP_LOW TEMP_HIGH with sensors connected to the indoor temperature detection terminology.
Verilog HDL设计练习进阶
- 初学verilog HDL时 找的好资料 大家共享-Beginners should try to find a good share information
pcm
- 该程序设计了一个产生PCM码流时序信号的模块,他包括输入端CLK,SET及输出端Q1,Q2,Q3-the program have designed a PCM signal timing modules, including the CLK input, and output SET Q1, Q2 and Q3
codestream
- 设计一个模块,从一个窜行数据流里检测出码流“11100”,这个模块包括reset,clk,datain及输出端pmatch-design a module from a trip data flow channeling Lane detected bitstream "11100", this module includes reset, clk, datain and output pmatch
counter10
- 该程序实现的是10进制的计数器,具有置位复位的功能。-the program is the band of 10 counters, with the home-reset function.
sub_full_n
- 该程序实现的N位全减器,首先实现一位的减法器,之后实现N位全减器。-Program of the N-bit-wide reduction, the first realization of a subtraction for, after all N-reduction devices.