资源列表
avalon_slave_pwm
- NIOS环境PWM的USER LOGIC实例1-NIOS environment PWM USER an example LOGIC
vhdl_vga_kb
- VHDL的显示驱动程序，VHDL的PS2键盘驱动程序-VHDL display drivers, VHDL PS2 Keyboard Driver
双路脉冲发生器（veralog）
- Verilog HDL 程序 双路脉冲发生器的代码 包含了键盘控制，LED显示，脉冲发生，脉冲频率测量模块 是我自己写得，希望能对你有帮助，有问题可以mail：shaojunwu1@163.com-Verilog HDL dual-channel pulse generator procedure code includes a keyboard control, LED display, pulse, pulse frequency measurement module is wr
edajishu
- ＥＤＡ基础教程-EDA based tutorial.
自动打铃系统
- 自动打铃系统，在ＭＡＸＰＬＵＳ平台下动行，能实现计时、打铃控制等功能。 -automatic bell system, the Converter Platform animal, able to plan, a Bell controls.
VHDL 的实例程序，共44个
- 经典VHDL 的实例程序，共44个！要下载的尽快-classic examples of VHDL, with a total of 44! To download as soon as possible
PLI
- VCS下编译通过的PLI的实例，包括功能仿真，和可综合代码-VCS compiled under the pli example, including the functional simulation, and integrated code
fifo1616
- FIFO先入先出堆栈，包括三个子程序，可根据需要选择-FIFO first in-first stack, including three subprogram, according to choose
RISC8.ZIP
- 简单的一个8位RISC，Verilog HDL代码,类型为pic16c57-a simple eight RISC, Verilog HDL code, the type of pic16c57
micro uart
- 硬件uart源程序verilog HDL，即相关文档-hardware UART Verilog HDL source, that the relevant documents
八位的伪随机数产生的verilog文件
- 八位的伪随机数产生的verilog文件linear-feedback-shift-register-eight pseudo-random number generator in Verilog document linear-feedback - shift-register
数据选择器vhd源代码
- 数据选择器，半加器，3-8译码器vhd源代码。是最近学校的实验内容。我要成会员，所以都发上来供大家参考。-data selection, half-adder ,3-8 decoder vhd source code. Recent experimental schools content. I want to become members and therefore has made onto for reference.