搜索资源列表
uart8.zip
- 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。,Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to sta
AteralIP.rar
- Altera IP核8B10B编码器的完整设计流程包括Altera IP的定制、仿真和实现的全过程,Altera IP core of the integrity of the 8B10B encoder design process, including the Altera IP customization, simulation and realization of the whole process of
sdramcontroller.rar
- 最完整的SDRAM控制IP核，包括源代码，仿真文件，以及IP核描述文件，包你用得上,SDRAM control of the most complete IP core, including source code, simulation, as well as IP core descr iption files, it can be helpful
DDS.rar
- 实现函数波形发生器的功能，内有用自己编的源代码实现的，也有用quartus的IP核实现的。,The realization of the function waveform generator function, useful for their own realization of the source code, it also uses the IP core quartus achieved.
altera_up_avalon_sd_card_inter
- 基于VHDL的SD卡IP核，Altera公司推出的大学计划！最新版本9.0,VHDL-based IP core of the SD card, Altera' s university program launched! The latest version 9.0
USB2.0-IP-core
- 用verilog 写的USB2.0，含源码。从别处找来的，不敢独享，希望对大家有帮助-Written by verilog USB2.0, including source code. Recruited from elsewhere, and not exclusive, we want to help
sd_card
- 面向altera公司的大学计划sd-card ip核，检测sd卡是否插入卡槽中。-Altera company s University Program for sd-card ip core, testing sd card is inserted into the card slot
ISE_lab17
- 本实验使用 XILINX 提供的IP 核，并例化该IP 核来实现正弦信号发生器的功能。由于 ISE 中有DDS（Direct Digital Synthesizer 5.0）IP 核，因此只需要编写一个顶层文件来调用 Core Generator 生成的IP 即可。-This study provides the IP core using the XILINX, and cases of the IP core to achieve the sinusoidal signal gene
ram_fifo_ram
- 程序实现了在FPGA内部开辟RAM+FIFO+RAM的IP核进行数据之间的调试。方便需要用到的童鞋进行参考。已通过modelsim调试-Implemented within the FPGA program to open up RAM+ FIFO+ RAM for data between the IP core debugging. Need to use the shoes for easy reference. Has passed debug modelsim
CAN_IP.rar
- 这是CAN总线控制器的IP核，源码是由Verilog HDL编写的。其硬件结构与SJA1000类似，满足CAN2.0B协议。,This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
USB_Verilog_IP
- USB IP核VHDL源码(使用VHDL实现的USB IP core)-USB IP core VHDL source
xsp605_ilinx_mig_ipcore
- 赛林思开发板sp605的内存管理单元的ip核调试通过-SP605 IP core mig
dds_test.rar
- 此程序在于，调用ISE中自带的DDS__IP，来产生单正弦信号，该程序已通过布线后仿真实现,The program focus on that it utilize the DDS core embedded in the ISE to generate the sigle sinusoid signal and this program have acess to the posted simulation!
AlterMCU8051IP
- 8051IP核 FPGA ALTER公司-8051IP-core FPGA
fsk
- 用Verilog实现FSK调制，调用IP核实现正弦余弦的调制-Verilog implementation using FSK modulation, called IP core to achieve the modulation sine cosine
HDLC
- verilog HDL语言编写的HDLC协议的IP核，包括通讯控制及CRC。-written in verilog HDL HDLC protocol IP core, including communications control and CRC.
CIC
- CIC IP core实现结构中自动生成的接口代码,基于软件无线电的应用，在毕业论文中已使用过。-CIC IP core to achieve the structure of the interface code automatically generated, based on software radio applications, has been used in the thesis.
FLASH
- SST39VF400A的IP核，可直接用于microblaze的应用里，在合众达FEM024直接使用-SST39VF400A the IP core, can be used directly microblaze applications, the direct use in the Triangle over FEM024
fftipcore
- Quartus 中fft ip core 的使用-FFT
fft
- 基于VHDL语言编写的FFT程序，256点，旋转因子存在自己编写的ROM里面，乘法器和数据存储采用的是IP核-FFT-based program written in VHDL, 256 points, there is rotation factor which I have written the ROM, multiplier, and data storage is used in IP core