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multiply
- Verilog hdl语言 常用乘法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used multiplier design, can use the ModelSim simulation
SDRAM
- SDRAM控制器，Verilog代码编写，让你快速了解SDRAM的读写时序。包含Modelsim仿真工程和学习笔记-SDRAM controller, Verilog coding, allows you to quickly understand the SDRAM read and write timing. Modelsim simulation engineering and contains study notes
UART
- 语言：verilog语言 功能：通过串口控制模块，实现FPGA与串口 通信。 仿真环境：modelsim 综合环境：quartus -Language: verilog language function: through the serial port control module, FPGA and serial communication. Simulation Environment: modelsim integrated environment: quartu
verilog_sdram
- SDRAM读写控制的实现与Modelsim仿真,采用verilog HDL编写-sdram controller and simulate with modelsim
PcodeGeneration
- 在ModelSim或其他支持Verilog语言编译的环境中仿真可得GPS的P码及与卫星数据码调制后的波形，其中一个为源程序，另一个为测试程序-ModelSim or other support in the language Verilog simulation environment to compile available GPS P-code and code of satellite data after the modulation waveform, one for the sour
ddrsdram_verilog
- 内附doc是DDR SDRAM 参考设计文档；model包含SDRAM Verilog的模型；simulation包含verilog测试平台、modelsim工程文、设计库函数；source包含verilog源文件；synthesis包含工程的综合文件 。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM Verilog model simulation with veri
SDRAM_CONTROLlER_Modelsim
- SDRAM控制器，Verilog代码编写，让你快速了解SDRAM的读写时序。包含Modelsim仿真工程和文档-SDRAM controller, Verilog coding, allows you to quickly understand the SDRAM read and write timing. Modelsim simulation engineering and contains study notes
LFSR
- verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) mo
FFT
- Verilog实现的FFT模块，供OFDM调制系统使用，可供大家参考学习-Verilog implementation FFT module for the OFDM modulation system used for your reference study
test_pll
- 使用modelsim se6.5d仿真altpll锁相环 完整工程，verilog代码，因为没找到选的是vhdl-simulation pll with modelsim se6.5d
4bit_buma_adder
- Verilog作业 ：自己写的源码输入，补码输出的，由状态机控制的四位加法器，为保证时序，加法器模块为超前近位加法器，包含测试台，通过 Modelsim 、Synplify仿真。-Verilog operation: the source code to write their own input, complementary code output by the state machine to control the four adder, in order to ensure timing
add
- Verilog hdl语言 常用加法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used adder design, can use the ModelSim simulation
GFmultiply
- Verilog hdl语言 伽罗华域GF（q）乘法器设计，可使用modelsim进行仿真-Language Verilog hdl Galois field GF (q) multiplier design, can use the ModelSim simulation
ADC_INTERFACE
- it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit. -it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix i
FIFO
- it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a
16bitCLA
- 基于Verilog HDL的16位超前进位加法器 分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules
mc8051_design
- 8051内核的设计，用Verilog硬件描述语言实现，在modelsim环境下进行仿真。-8051-core design, using Verilog hardware descr iption language, in the modelsim simulation environment.
IIRtest
- quartusII9.0开发环境下巴特沃斯IIR滤波器的实现完整的工程文件，同时里面有文档详细说明如何用modelsim对altera芯片进行仿真-development environment quartusII9.0 Butterworth IIR filter to achieve a complete project file, but there are documents in detail how to use modelsim to altera-chip simulation
CPU_reference
- 采用verilog语言描述的 arm7架构处理器。 使用quartusII+modelsim se 进行开发和验证-Using verilog language to describe the arm7-based processors. Use quartusII+ modelsim se for development and validation of
LCD
- lcd verilog hdl 源码 可以直接使用，适用modelsim-lcd verilog HDL source