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seg
- 六位十六位进制数可逆循环计数器、七段译码器设计,完全有VHDL语言设计,生成SYM文件后,设计top.gdf文件,赋好管脚下载到altera芯片上执行。-Sixteen decimal six reversible cycle counter, seven-segment decoder design, fully VHDL language design, build SYM files, design top.gdf file, assign a good pin downloaded to
vhdl--eda
- m 序列发生器 计数器 七段数码管显示 bcd 十六进制转换-failed to translate
VHDL_counter
- 实验要求:用VHDL语言设计一个16进制加减计数器,计数方向可以由外界输入信号控制,带有清零和置位,输出除了包括计数值外还应包括进位和借位。-Design a VHDL counter
CPLD
- 设计一个6进制递增计数器,计数信号通过K0产生并输入。计数结果利用试验仪上的数码管LED2显示。-Design a 6 hexadecimal increment the counter, and enter the count signal generated by K0. Count results on the tester digital tube display LED2.
kt1
- 基于FPGA的可控100进制可逆计数器,运行环境maxplus-Controlled 100 hex reversible counter FPGA-based operating environment maxplus
counter
- VHDL 脉冲输入15进制输出计数器 计数器是实际中最为实用的时序电路模块之一-VHDL pulse input the counter of the output of the 15 hexadecimal counter the one of the of yes one of the the actual in the the most practical timing circuit module
zonghe
- 实现12进制异步计数器,内置分频模块,可以下载到单片机上查看结果-12 hex asynchronous counter, built-in frequency module, can be downloaded to view the results on the single-chip
Counter
- 计数器,五进制的计数器,在此基础上可以做十进制,六十进制等的计数器.-Counter quinary counter, can be done on the basis of the decimal, six decimal, such as the counter.
shuzhizhong(vhdl)
- 数字钟设计 计时计数器用24进制计时电路; 可手动校时,能分别进行时、分的校正; 整点报时; 选做:可设置闹时功能,当计时计到预定时间时,扬声器发出闹铃信号,闹铃时间为4s,并可提前终止闹铃。-Digital clock design
VHDL_60-system_counter
- 用VHDL语言编写的简易60进制的可调节计数器,用于Xilinx ISE软件-A 60-digit system settable countr using VHDL, programming using Xilinx ISE
jishuqi
- EDA实现计数器功能十六进制和二十四进制-EDA counter function hex and 24 quaternary
cnt
- 4位及8位计数器,根据4进制和8进制原理设计计数器-4位及8位计数器,根据4进制和8进制原理设计计数器 您是不是要找: jk触发器,根据输入的信号的产生相应的输出 请键入文字或网站地址,或者上传文档。 取消 4 Wèi jí 8 wèi jìshùqì, gēnjù 4 jìn zhì hé 8 jìn zhì yuánlǐ shèjì jìshùqì “”的用法示例:由 Google 自动翻译英语中文(简体)日语4-bit and 8-bit counter, hexade
Eight-16-band-frequency-meter-design
- 8位16进制频率计的设计,其中包括测评控制电路的设计,32位锁存器的设计,32位计数器的设计和频率计顶层文件-Eight 16-band frequency of the design, including the design of the evaluation of the control circuit, 32-bit latch design, the design of 32-bit counter and frequency meter top-level document
counter
- 频率计的一个模块,即计数器,六进制和十进制级联,构成六十计数器-Frequency of a module, counter, hex and decimal cascade of constitute sixty counter
clock
- Verilog 编写的60进制的计数器,可以用来设计数字钟、频率计等-count_60 for digital clock using Verilog
count-1
- 基于Verilog的仿真,各个进制的计数器仿真。-Verilog-based simulation, the simulation hex counter.
VHDL
- VHDL初级编程实例:动态扫描显示程序、分频器设计程序、8位移位寄存器、BCD计数器设计(任意进制)等等。-VHDL the primary programming examples: dynamic scanning display program, the divider design process, the 8-bit shift register, BCD counter design (any hex), and so on.
shijinzhi.c
- 10进制同步计数器,带一个清零端,一个进位输出端-10 N synchronous counter with a clear side, a carry output
clock
- 设计一台能显示时、分、秒的数字电子钟,具体要求如下: (1)时计数器用24进制计时电路,分、秒计数器用60进制计分、计秒电路; (2)可手动校时,能分别进行时、分的校正; (3)能实现整点报时功能。 -Design a table can display hours, minutes and seconds of digital electronic clock, the specific requirements are as follows: (a) when the cou
Digital-clock-design
- 数字钟设计 用VHDL实现一个50MHZ到1HZ的分频器,利用Quartus II进行文本编辑输入和仿真硬件测试。实现一个60进制和24进制的计数器。测试成功。-Digital clock design using VHDL a 50MHZ to 1HZ divider using Quartus II simulation for text input and editing hardware test. Achieve a 60 hex and 24 hex counter. Test wa