搜索资源列表
FIFO
- verilog编写的读写fifo的源码,包括sram的读写控制-verilog source code written to read and write fifo, including the sram to read and write control
FIFO
- 用verilog实现异步FIFO,代码中有两个模块,使用时注意顶层模块和底层模块,用quartus2即可打开直接使用。-Verilog using Asynchronous FIFO, the code has two modules, when the attention of top-level module and the bottom module, with direct access to open quartus2.
lcd-code
- 比较完整的LCD接口代码,verilog编写,分为6800和8080两种CPU接口,且有完整的仿真程序-Relatively complete LCD interface code, verilog prepared 6800 and 8080 is divided into two types of CPU interfaces, and there is a complete simulation program
fifo的vhdl原代码
- 本文为verilog的源代码-In this paper, the source code for Verilog
FIFO
- 通用异步FIFO设计的verilog代码,来自于opencore-Universal Asynchronous FIFO Verilog design code, from opencore
asyn_fifo
- verilog编写的异步fifo源代码,asyn_fifo.v为顶层,调用其他四个文件-asynchronous fifo prepared Verilog source code, asyn_fifo.v for top-level, call the other four documents
FIFO
- it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a
fifo_ptrs_gray
- fifo pointers in verilog gray code utilization for synchronius
8fifo
- 可综合的 8x8 fifo VHDL 源代码-Can be integrated 8x8 fifo VHDL source code
fifo
- a_fifo5.v verilog code for asynchronous FIFO-a_fifo5.v verilog code for asynchronous FIFO
Memory
- Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
FIFO_Buffer
- Verilog的FIFO源代码,可综合,并以运用到具体工程中-Verilog source code of the FIFO can be integrated and applied to specific projects
async_fifo
- verilog HDL写的异步fifo代码及测试平台,直接可用,可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
FIFO
- FIFO的VERILOG代码编写 可综合的Verilog FIFO存储器-The VERILOG code FIFO write comprehensive Verilog FIFO memory
FIFO
- 异步FIFO Verilog源代码,对控制读写地址进行设计,以便写满和读空只产生一个标志,实现对FIFO的缓冲控制-Asynchronous FIFO Verilog source code, designed to control read and write addresses in order to fill and read empty produce only one flag, the FIFO buffer control
FIFO
- Verilog代码,实现FIFO先入先出存储-FIFO CODE,VERILOG
FIFO
- FIFO is accomplished with the code which is written using the language of verilog.FIFO is the means of first output while first input
fifo-code
- Verilog代码:同步\异步FIFO。包含格雷码计数器.-Verilog code: syncronous\asyncourous FIFO. containing gray counter.
fifo
- 基于verilog HDL的fifo设计与测试,包含设计与测试代码,以及简单的makefile编写。整个平台是基于linux操作,仿真平台是基于SYNOPSYS的vcs工具。(Based on verilog HDL fifo design and testing, including the design and test code, and simple makefile.The platform is based on Linux operating, the simulation pla
FIFO
- FIFO code in verilog