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使用verilog编写的交通灯控制程序，各方向通行时间可调，绿灯5s闪烁，在maxplus下调试通过，附仿真波形，在EP系列实验板上测试成功-use Verilog prepared by the traffic lights control procedures, the passage of time adjustable direction, green 5s flickered in maxplus under debugging, simulation waveforms with t
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A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation results. A co-design example of C and Verilog.
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A code writing by Verilog which can find medium value. With a C file to see the simulation results. A co-design example of C and Verilog.
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As the source code name, this code is writing in Verilog and also inside the folder there is a c code to see the simulation results from verilog.
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Verilog-RISC CPU 代码
实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。
北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware descr iption language, and design methods. The procedure adopted
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关于YUV转RGB的verilog源代码、说明文档和modelsin仿真，相信对大家一定有很大的帮助，我费了好长时间才找到的！-YUV to RGB on the verilog source code, documentation and modelsin simulation, we believe that there will be a great help, I spent a good long time to find it!
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verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) mo
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本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure an
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RS(204,188)译码器说明
原文件：
rs_decoder.v（顶层文件）, SyndromeCalc.v（计算伴随式）, BM_KES.v（BM求解关键方程）,
Forney.v（Forney算法求误差样值）, CheinSearch.v（搜索错误位置）,ff_mul.v（有限域乘法）。
ROM及初始化文件：
rom_inv.v（求逆运算）, rom_power.v（求幂运算）；
rom_inv.mif（ROM初始化文件）, rom_po
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用Verilog实现卷积码（2，1，2）的编码器，采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the
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本人写的MSK解调位同步完整程序，基于QuartusII90环境，采用verilog语言编写，程序简练，可靠性高，而且暂用资源少，适合CPLD器件。文件包含仿真和说明，欢迎下载！-I write a complete program MSK demodulation bit synchronization, based on QuartusII90 environment, using verilog language, procedures, concise, high reliability
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串口verilog代码，包括测试环境，仿真环境。-SPI design，verilog code，incude test and simulation scr ipt。
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FPGA描述I2C协议过程，采用Verilog语言编写，压缩包里含有完整的代码（已经综合仿真），仿真图-FPGA I2C protocol process descr iption, using Verilog language, compressed bundle contains the complete code (already integrated simulation), simulation map
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serial simulation receiver in verilog
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ddr3相关代码和基于ISE仿真调试，板级调试(DDR3 related code and simulation debugging based on ISE, board level debugging)
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格雷码计数器实质包含了三个部分 格雷码转二进制、加法器、二进制转格雷码。通过quartus II 自带的Modlesim仿真验证了 能够实现二进制和格雷码之间的转换(Gray counter essence contains three parts, gray code to binary adder, binary gray code conversion. Modlesim simulation by quartus with II verified to achieve the conve
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基于quartus II的CRC16校验代码，并实现了Modlsim实现了仿真验证(The CRC16 check code based on Quartus II and the realization of the simulation verification by Modlsim)
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Verilog代码实现数据流输入检测，并综合仿真(Verilog code implements data flow input detection and integrated simulation.)
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关于彩屏（TLT）驱动的编写，实现彩屏的显示，工程在quartus13中建立，包括了仿真设计(About the color screen (TLT) driver's preparation, the realization of the color display, the project was established in quartus13, including the simulation design.)
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SD卡的SPI模式verilog代码，外加modelsim仿真结果。(SD card's SPI mode Verilog code, plus the simulation results of modelsim.)
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