搜索资源列表
I2Cdesign.rar
- I2C总线Verilog源代码描述，ModelSim仿真,I2C bus Verilog source code descr iption, ModelSim Simulation
RiscCpu
- Verilog-RISC CPU 代码 实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。 北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware descr iption language, and design methods. The procedure adopted
how-to-use-modelsim
- 逐步演示试用modelsim建立仿真的过程，初学者应该-Step by step demonstration of the trial to establish modelsim simulation process, beginners should look at the
VHDL
- 含有常用组合电路模块的设计和应用这个实验所需的VHDL的代码，用modelsim仿真并建立了ISE文件-VHDL code module containing commonly used combination of circuit design and application required by this experiment, the simulation with modelsim and ISE file
DAGC(fpga)
- 在fpga中实现DAGC，并用modelsim仿真输出-The fpga in DAGC, and with modelsim simulation output
code
- 是用verilog写的带uart的简单controller，使用的是mips指令，用modelsim仿真，波形正确-With uart verilog write a simple controller, use the mips instruction the modelsim simulation, waveform correctly
da_fir
- 基于FPGA分布式算法FIR滤波器verilog代码 （本人 小论文 代码，通过验证） 本文提出一种新的FIR滤波器FPGA实现方法。讨论了分布式算法原理，并提出了基于分布式算法FIR滤波器的实现方法。通过改进型分布式算法结构减少硬件资源消耗，用流水线技术提高运算速度，采用分割查找表方法减小存储规模，并在Matlab和Modelsim仿真平台得到验证。 为了节省FPGA逻辑资源、提高系统速度，设计中引入了分布式算法实现有限脉冲响应滤波器(F
DCFIFO
- DCFIFO 的modelsim仿真工程，已经写好激励，可以直接使用modelsim观察波形-DCFIFO test
LineBuffer
- Verilog HDL的移位寄存器的modelsim仿真
sim
- i2c代码及modelsim仿真，可以读写eeprom。-i2c code and modelsim simulation, can read and write eeprom.
Trafficlights
- 交通灯控制程序，基于Quartus开发，附带测试程序，基于modelsim仿真-traffic lights
3
- 对Modelsim仿真生成数据的写入文件，然后在Matlab中在把这个文件的数据读出来。-Modelsim simulation for generating the data written to the file, and then in Matlab to read the data in the file out.
test_uart
- verilog 编写的串口发送和接收模块，能够设定停止位和校验位，并且包含了modelsim仿真文件。-verilog prepared by the serial port to send and receive module, capable of setting the stop bit and the parity bit, and includes modelsim simulation files.
design
- 双口ROM的设计与数据处理，亲测可用，modelsim仿真-Design and data processing dual-port ROM, the pro-test available, modelsim simulation
fft_streaming
- 关于QuartusII FFT ip核的使用，采用Streaming模式，包含Modelsim仿真程序-About QuartusII FFT ip nuclear use, using Streaming mode, including Modelsim simulation program
FPGA_programming_simulation
- 有关FPGA硬件开发的学习参考资料，包括FPGA_CPLD和Modelsim仿真-FPGA hardware development related learning references, including FPGA_CPLD and Modelsim simulation
cpu_me
- 采用verilog编写的cpu,modelsim仿真均实现8条指令功能，有虚拟ram和rom-Using verilog prepared cpu, modelsim simulation functions are to achieve eight instructions, there are virtual ram and rom
second-and--minite-and-hour-counter
- 利用Verilog语言实现时分秒计时功能，并用modelsim仿真出波形。-implementate when minutes timing function using Verilog language, and simulating waveform in the modelsim
union simulation of Simulink and modelsim
- 详细介绍了Simulink和modelsim联合仿真的方法与流程。(The method and process of joint simulation of Simulink and Modelsim are introduced in detail)
SD SPI模式verilog外加modelsim仿真结果
- SD卡的SPI模式verilog代码，外加modelsim仿真结果。(SD card's SPI mode Verilog code, plus the simulation results of modelsim.)