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uart(Verilog)
- RS232的verilog源代码,如果需要的可以
曼彻斯特编解码Verilog代码
- 曼彻斯特编解码Verilog代码 .zip-Manchester codec Verilog code. Zip
ddc_scl_detect
- 显示器ddc数据通道的时钟和数据信号检测的Verilog代码。
verilog tutorial
- verilog实例教程
cic code Verilog代码
- cic code选用verilog代码编写
FPGA与USB通信的测试代码
- FPGA与USB通信的测试代码，包括FPGA中的程序（Verilog编写）和PC机上的主控程序以及USB固件程序。,FPGA and the USB communication test code, including the FPGA in the procedure [Verilog prepared] and PC-control procedures, as well as the USB firmware.
16QAM_verilog 使用Verilog实现全数字的16QAM调制器
- 使用Verilog实现全数字的16QAM调制器，假设载波的频率为1MHz，数据比特率为100kbit/s.包括源代码和testbench-use verilog to realize 16qam,carrier frequency is 1MHz,data rate is 100kbit/s.including source code and testbench
decode.rar
- LDPC的Verilog程序源代码，包括仿真数据等。文件很大，请慢慢下载,LDPC of Verilog source code, including the simulation data. Large file, please download slowly
spi
- SPI master的verilog代码-Verilog code for SPI master
asfifodesign
- 异步fifo设计文档，里面包括详细的verilog设计方案及代码。fifo设计是通信中必然设计的设计-a fifo design with code inside, using verilog language
uart
- 串口通讯 PC发送FPGA接受后回传 verilog语言-uart verilog
UART
- 本人自己编写的FPGA异步串口通信模块（UART），基于QuartusII环境，verilog语言编写，包含仿真和全部程序及说明，验证通过，具有很好的稳定性和参考价值！-I have written of the FPGA asynchronous serial communication module (UART), based on QuartusII the environment, verilog language, including simulation and all the pr
verilog
- 采用用verilog语言编写的全数字锁相环的源代码。-Verilog language used by all-digital phase-locked loop' s source code.
decoder
- 用verilog编写的bch译码器，包括测试文件，随机加载了比特流，进行了测试。-Prepared using Verilog BCH decoder, including test papers, random load the bit stream to carry out the test.
RS232(verilog)
- 串口RS232通信程序，包括对串口通信原理的说明。-RS232 serial communication program, including a descr iption of the principles of serial communication.
viter2
- verilog实现卷积码的译码，viterbi算法-verilog to achieve the decoding convolutional codes, viterbi algorithm
FPGA-RS232-verilog
- fpga上的串口驱动程序，包括接收主机来的数据（deserial）和发送由FPGA产生的数据(serial).该程序的调试需要借助串口调试助手-serial port driver on the fpga, including the receiving host to the data (deserial) and send the data generated by the FPGA (serial) to pc. The program needs the serial debug deb
verilog
- 介绍了一种SPI从机的接口verilog编码-verilog code for spi slave
8b10b Verilog
- 采用verilog语言基于查找表描述8b10b编码源代码(Using Verilog language to describe 8B10B encoding source code based on look-up table)