搜索资源列表
decode.rar
- LDPC的Verilog程序源代码，包括仿真数据等。文件很大，请慢慢下载,LDPC of Verilog source code, including the simulation data. Large file, please download slowly
H_2048x4096
- LDPC 码二进制规则码生成矩阵2048*4096，效果很理想-LDPC code rules binary code generated matrix 2048* 4096, the effect is very satisfactory
Verilog_module
- Verilog编写基于FPGA的鉴相器模块-Write Verilog FPGA-based phase detector module
H_512x1024
- LDPC 码二进制规则码生成矩阵512*1024，效果很理想-LDPC code rules binary code matrix to generate 512* 1024, the effect is very satisfactory
GSM_DDC
- GSM中数字下变频器的matlab辅助设计，并可以采用matlab生成verilog代码。-GSM digital down converter in the matlab-aided design, and can be used matlab generate verilog code.
dhpi
- 接口设计，描述硬件与fpga的接口程序，使用verilog语言-Interface design, describe the hardware and fpga interface program, use the verilog language
Channel_Equalizer
- 802.11a接收机的信道均衡源码，verilog语言的-802.11a receiver channel equalizer source, verilog language
Sampling_Frequency_Synchronization
- 802.11a接收机的采样频率同步源码，verilog语言的-802.11a receiver sampling frequency synchronization source, verilog language
SPI
- 该程序是SPI的verilog程序，经过我的调试，是可以直接用的。-The program is SPI, verilog procedure by going through my debugging, it can directly use.
8B10B
- 8B10B编解码的较为详细的介绍，8B10B是目前的很多通信网络采用的编解码标准。-8B10B encoding and decoding of a more detailed introduction.
c10
- 用Verilog编的，用FPGA实现3G手机，属于软件无线电在WCDMA中应用-USE FPGA design 3G phone （WCDMA）by verilog
DDFS_verilog
- 直接数字频率综合器，采用ROM压缩法，经过FPGA验证和AISC实现-Direct digital frequency synthesizer, using ROM compression method, validation and AISC through FPGA Implementation
LMS
- verilog实现的LMS的算法，另外有tb文件可以测试已测试代码正确-verilog implementation of LMS algorithm, another tb files can test the code has been tested properly ......
BCH_dec_verilog
- BCH decoder based on Verilog design
gsm_ddc
- 基于GSM的数字下变频代码，能够直接生成Verilog代码，需要Synplify DSP 支持。-GSM DDC code. This Model can directly generate RTL code via Synplify DSP.
BPSK_receiver
- BPSK接收机设计，能够通过Synplify DSP直接生成Verilog代码。-BPSK Reciver model. This simulink model can generate RTL code via Synplify DSP.
XOR_tree
- This source code is a check node unit for LDPC decoder. The language is Verilog HDL.
95b4abf558734ca9a899a0b792ce3f84
- OFDM的接收机代码，使用Verilog写的，搬运(Receiver code for OFDM)