搜索资源列表
Wishbone
- wishbone总线协议详细的技术说明文挡！-wishbone bus protocol detailed technical descr iption of the text block!
wishbone_VHDL.rar
- wishbone总线的VHDL源代码 wishbone适用于与FPGA中IP核的高速通信，其接口简单，速度快 成为ip通信的主流,Wishbone Bus VHDL source code Wishbone applicable to IP core in FPGA high-speed communications, and its easy interface, fast becoming the mainstream of ip communications
SDCard_Controller.rar
- SD卡控制器IP. 兼容SD卡协议2.0。与wishbone bus 接口，方便与其他IP连接使用。 ,SD Card Controller IP. Compatible with SD Card Agreement 2.0. With the wishbone bus interface to facilitate the use of other IP connections.
pci.tar.gz 完成WB BUS和PCI bus之间的传输
- verilog编写的PCI总线，提供了Wishbone bus和PCI local bus之间的接口，内由两个独立的模块组成，分别完成WB BUS和PCI bus之间的传输,The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus and the PCI local bus. It consists of two independent units, one handling transact
wbspec_b4
- wishbone总线的规范介绍，很详细，很不错-wishbone bus specification describes, in great detail, very good
SoCWishboneSystem
- SoC-Wishbone System IP核的VHDL语言源代码-SoC-Wishbone System IP core language VHDL source code
wishbone_i2c_master_vhd
- wishbone i2c master vhdl code
spi_wishbone
- spi wishbone bus code
ethernet.tar
- VHDL MAC wishbone VHDL MAC wishbone-VHDL MACVHDL MAC wishbone VHDL MAC wishbone
ahb2wishbone_latest.tar
- opencore ahb to wishbone bus verilog code
ima_adpcm_encoder_latest.tar
- This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by defau
i2c
- 基于wishbone总线的I2C的ip核，可供学习和参考．-I2C Bus-based wishbone of ip core, available for study and reference.
This_is_pci-wishbone_nuclear_and_16450_serial_port
- 这是用pci-wishbone核和16450串口核在xilinx的FPGA上实现的。-This is pci-wishbone nuclear and 16450 serial port on the nucleus in xilinx FPGA-implemented.
wishbone_m4_s8
- wishbone 骨幹部份 RTL 源碼, 以verilog 寫成, 自創. 支源 4 master 及 8 slave-wishbone core, write by verilog, support 4 master and 8 slaver. language: verilog.
vga_lcd_latest.tar
- 此VGA/LCD控制器是revB.3版本的基于WISHBONE总线，适用于驱动CRT和LCD显示屏的嵌入式VGA驱动。-VGA/LCD Controller core is a WISHBONE revB.3 compliant embedded VGA core capable of driving CRT and LCD displays. It supports user programmable resolutions and video timings, which are limit
UART_IP_core_for_wishbone
- 基于wishbone总线的UART IP core-UART IP core based on Wishbone, generated in Verilog HDL.
ahb2wishbone_latest.tar
- AHB总线到wishbone总线的转化的Verilog源码-AHB to wishbone verilog source code
wb_to_amba_latest.tar
- wishbone总线到AMBA总线的转换，做总线的朋友可以-wishbone bus to the AMBA bus conversion, so friends can see the bus
wb_conmax_latest.tar
- WISHBONE总线的接口实现，采用Verilog完成。能同时连接8个主设备和16个从设备。-WISHBONE bus interface, the use of Verilog to complete. Can simultaneously connect up to 8 masters and 16 slaves.
wishbone
- wishbone IP CORE Verilog quartus-wishbone IP CORE Verilog quartusii