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counter&adder
- counter and adder program by vhdl. Just enjoy it!-counter and adder program by VHDL. Just enj oy it!
add(FLP).32位元的浮点数加法器
- 一个32位元的浮点数加法器,可将两IEEE 754格式内的值进行相加,A 32-bit floating-point adder can be both within the IEEE 754 format to add value
adder.rar
- 一位全加器可由两个一位半加器与一个或门构成,该设计利用层次结构描述法,首先设计半加器电路,将其打包为半加器模块;然后在顶层调用半加器模块组成全加器电路,A full adder can be two a half-adder and an OR gate structure, the design is the use of hierarchical descr iption method, first of all the design half-adder circuit, be packa
hdl-hw1-brent-kung-adder
- BRENT KUNG ADDER 4 bits
adder
- 高达16位加法器的实现,工作环境在ISE,modesim,该例程较为详细!-Up to 16-bit adder implementation, the working environment at ISE, modesim, the more detailed routines!
adder
- 加法器 可做4BIT的運算 用直接語言撰寫-Adder computing can 4BIT
adder
- 采用加法树流水线乘法构造八位乘法器,并分析设计的性能和结果在时钟节拍上落后的影响因素。 -Multiplication using adder tree structure line 8 multiplier, the design and analysis of the results of the performance and beat the clock on the impact of the factors behind.
adder
- verilog 加法器设计 在modelsim下方针-verilog adder
ADDER
- simple 16-bit CSA Adder
Floating-Point-Adder
- 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算,结合vhdl和EPGA可编程技术,完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmab
floating-point-adder
- verilog implementation of the floating point adder
VHDL-ripple-lookahead-carryselect-adder
- vhdl code for ripple carry adder, carry select adder and carry look ahead adder
32-rip-adder
- A ripple carry adder allows you to add two 32-bit numbers
16-bit-adder
- 这是关于16位加法器的实现代码及仿真图形的压缩文档-This is about 16-bit adder implementation code and simulation graphics archive
Optimized-design-of-BCD-adder-and-Carry
- Optimized design of BCD adder and Carry
Verilog Full Adder
- This is some real adder type stuff. To the fullest degree.
2-bit-full-adder-master
- full adder 4 bit one you
Carry-Skip Adder
- 经典的进位跳跃、进位选择、并行前缀加法器,16位,基于verilog HDL语言(16-bit carry-skip adder)
Half-Adder
- This is an example to implement an Half-adder for xilinx FPGA
Half-Adder
- xilinx ISE平台提供1位半加法器,模块随模拟提供(Half- adder 1- bit design implemented in ISE XIlinx Design Suite. Module in VHDL language)