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AssignmentP3
- Assignment 3 Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption styles, i.e., behavioral, dataflow and structural descr iptions. (1) Synthesize and (2) simulate these models respectively in the environment of Xilinx
VERILOGHDL
- this a book about the verilog-hdl design and circuit simulation and synthesize example
ADC_INTERFACE
- it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit. -it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix i
FIFO
- it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a
traffic_controller
- it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.-it is a verilog code written for traffic light controlle
UART_for_FPGArar
- it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]-it is a verilog code written for MELAY state machine based UART and it wll
DDSchuanxing
- dds ad9851 串行 输出 时序 程序基于c8051f-directly digital synthesize ad9851
asic_scrip_taiwan
- 台湾中山大学ASIC实验室综合脚本教程,对学习，编写ASIC综合脚本有很大帮助哈。-synthesize scr ipt guide for ASIC
FullAdder
- 要求在Quartus II软件，利用VHDL完成层次式电路设计，电路中的元件可以用VHDL设计也可以用库元件连线构成再封装。借助EDA工具中的综合器，适配器，时序仿真器和编程器等工具进行相应处理。输入方法不限制。适配采用Cyclone系列的EP1C6Q240C8。要求综合出RTL电路，并进行仿真输入波形设计并分析电路输出波形。要求采用层次式结构设计。-Quartus II software requires the use of VHDL complete hierarchical circui
AssignmentP6
- 1. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA. (1) Synthesize and verify (simulate) the VHDL design of the FIFOs (2) For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells)
2
- 在传统矩阵变换器和多电平逆变器的基础上,提出一种新颖的多电平矩阵变换器,介绍了其拓扑结构和工 作原理.多电平矩阵变换器的能量传递,是通过三相输入电压对中点电容充电到一个恒定直流电压而实现的.选择适 当的控制算法和电容电压,能在变换器的两侧合成低次谐波含量小且波形近似于正弦的可控输入/输出电压.对多电 平矩阵变换器进行建模和仿真,并探讨了其输出能控性. - On the basis of a conventional matrix converter and a multileve
FPGA-implementation-of-digital-filters-synthesize
- implement digital filter book. very useful.
Picoblaze1
- This a software to synthesize a microcontroller in a FPGA
synthesize--fit--simulation
- 关于FPGA 设计的流程过程的综合，适配，仿真名词的解释，以及相关注意事项-The attention of the process of FPGA
assigment3
- Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption styles, i.e., behavioral, dataflow and structural descr iptions. Synthesize and simulate these models respectively in the environment of Xilinx ISE with the Mod
01271048
- This paper presents neural networks based approach for estimation of the control and operating parameters of Statcom used for improving voltage profile in a power system, which is emerging as a major problem in the day-to-day operation of stresse
超声波电源程序基础
- msp430单片机计算频率控制字 然后将控制字传递给dds芯片合成高频电信号(The MSP430 microcontroller calculates the frequency control word, and then passes the control word to the DDS chip to synthesize the high frequency electrical signal)
alu
- Code to synthesize Arithmetic Logic Unit