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wb_lcd
- 基于wishbone的字符型lcd core，支持16×2的字符型lcd显示，verilog语言编写-character lcd core based Wishbone bus, support for 16 × 2' s character lcd display, verilog language
8
- 基于ADAMS的双横臂独立悬架的仿真分析及优化设计，作者：QQ 64134703 ，欢迎咨询-ADAMS-based double wishbone independent suspension of the simulation analysis and optimization design of: QQ 64134703, welcomed the Advisory
minsoc
- 片上处理器加上外设的设计,基于openrisc指令集，wishbone总线协议的一款基于FPGA的片上处理器-processor of on-chip
jtag_memory_v0.12
- JTAG调试接口与testbench，附加memory模块并支持cpu和wishbone-JTAG TAP with Controller and testbench ,and an addition of block memory and the potential support of cpu and wishbone
I2C
- 一个基于wishbone总线的I2C控制器以及测试文件-wishbone I2C
sdram_16bit_latest.tar
- 这个IP核是一个小型的，简单的SDRAM控制器，用于为16位SDRAM芯片提供32位流水线的二叉树接口。 当访问开放行时，读写可以流水线实现完整的SDRAM总线利用率，但是读写之间的切换需要几个周期。(This IP core is that of a small, simple SDRAM controller used to provide a 32-bit pipelined Wishbone interface to a 16-bit SDRAM chip. When acce