搜索资源列表
wishbone_VHDL.rar
- wishbone总线的VHDL源代码 wishbone适用于与FPGA中IP核的高速通信，其接口简单，速度快 成为ip通信的主流,Wishbone Bus VHDL source code Wishbone applicable to IP core in FPGA high-speed communications, and its easy interface, fast becoming the mainstream of ip communications
SDCard_Controller.rar
- SD卡控制器IP. 兼容SD卡协议2.0。与wishbone bus 接口，方便与其他IP连接使用。 ,SD Card Controller IP. Compatible with SD Card Agreement 2.0. With the wishbone bus interface to facilitate the use of other IP connections.
SoCWishboneSystem
- SoC-Wishbone System IP核的VHDL语言源代码-SoC-Wishbone System IP core language VHDL source code
wishbone_i2c_master_vhd
- wishbone i2c master vhdl code
ethernet.tar
- VHDL MAC wishbone VHDL MAC wishbone-VHDL MACVHDL MAC wishbone VHDL MAC wishbone
ima_adpcm_encoder_latest.tar
- This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by defau
i2c
- 基于wishbone总线的I2C的ip核，可供学习和参考．-I2C Bus-based wishbone of ip core, available for study and reference.
wishbone_m4_s8
- wishbone 骨幹部份 RTL 源碼, 以verilog 寫成, 自創. 支源 4 master 及 8 slave-wishbone core, write by verilog, support 4 master and 8 slaver. language: verilog.
vga_lcd_latest.tar
- 此VGA/LCD控制器是revB.3版本的基于WISHBONE总线，适用于驱动CRT和LCD显示屏的嵌入式VGA驱动。-VGA/LCD Controller core is a WISHBONE revB.3 compliant embedded VGA core capable of driving CRT and LCD displays. It supports user programmable resolutions and video timings, which are limit
UART_IP_core_for_wishbone
- 基于wishbone总线的UART IP core-UART IP core based on Wishbone, generated in Verilog HDL.
ahb2wishbone_latest.tar
- AHB总线到wishbone总线的转化的Verilog源码-AHB to wishbone verilog source code
wb_to_amba_latest.tar
- wishbone总线到AMBA总线的转换，做总线的朋友可以-wishbone bus to the AMBA bus conversion, so friends can see the bus
wb_conmax_latest.tar
- WISHBONE总线的接口实现，采用Verilog完成。能同时连接8个主设备和16个从设备。-WISHBONE bus interface, the use of Verilog to complete. Can simultaneously connect up to 8 masters and 16 slaves.
led_driver
- LED display verilog code. to generate clocks and wishbone interface
wishbone
- wishbone IP CORE Verilog quartus-wishbone IP CORE Verilog quartusii
AHB_to_Wishbone_Verilog
- 该源代码包是AHB总线到Wishbone总线的交接器，包括以下4个部分：RTL源代码，测试平台，软件测试程序，说明文档。-This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help documents.
wb_conbus
- wishbone的verilog代码的实现，标准的协议规范-wishbone of the verilog code implementation, the standard protocol specification
wishbone
- wishbone协议，IC设计必备 -wishbone agreement, IC design IC design must have the necessary
Digipot_wb_interface
- Generic Wishbone Slave interface for AD5204 driver. Instantiable in any platform.
uart_wb
- 兼容wishbone bus的uart模块，方便用户修改，时候初学者学习-Compatible with wishbone bus the uart module, user-friendly changes beginners to learn when