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divider.rar
- A divider implemented in VHDL
divider.8位的除法器
- 8位的除法器。用VHDL语言进行设计实现。,8-bit divider. With VHDL design languages.
div(FLP).rar
- 是Nios II處理器下客製化指令的一個32位元浮點數除法器，可將兩IEEE 754格式的值進行相除,Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division
FPGA_nCLK.rar
- VHDL语言的高频时钟分频模块。一种新的分频器实现方法。,VHDL language at the high-frequency clock frequency modules. Divider to achieve a new method.
div.rar
- 除法器实验 verilog CPLD EPM1270 源代码,Experimental divider verilog CPLDEPM1270 source code
divider
- 由VHDL撰写的强大多功能除频器，只需由上方参数载入除频数N及N的宽度(2的次方)即可使用。 可以除以任意整数，包含奇数。-Written by the powerful multi-functional VHDL divider, just above the parameters included in addition to the frequency width of N, N-(2 power) can be used. Can be divided by any integer,
divider
- 移位快速除法器，通过一次移4位试商实现快速除法功能，较普通减除法器有及其巨大的效率提升-Divider rapid shift by a shift to four test functions of rapid division, as compared with ordinary objects have less efficiency and its huge
verilog-divider-code
- Verilog编写的分频器程序，包括偶数分频和奇数分频，作为参考。-verilog divider code
32_16div
- 这是一个简单的除法器（32bit/16bit),采用移位相减法-This is a simple divider (32bit/16bit), using phase shift subtraction
Fredevider_n
- 任意N偶数倍频率分频器VHDL语言，编译器MAX_PLUS2-Any even multiple of the frequency divider N VHDL language, compiler MAX_PLUS2
divider
- verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。-verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.
divider
- 该模块为分频器，将1KHZ的时钟频率分频成每分钟一次的时钟频率 事实上，该源码可以实现任意整数的分频，主要让N的值设置好相应的数字-The module for the divider, the clock frequency 1KHz frequency per minute into the first clock frequency In fact, the source can be any integer frequency, mainly to allow the value o
div16
- 十六位的除法器，采用verilog hdl-16 of the divider using verilog hdl
clock_divider
- 任意小数分频器产生原理，及详细说明文档，任意数分频(包括奇偶数和小数)的设计方法(含VHDL例子)-Generate arbitrary decimal divider principle, and detailed descr iption of the document, arbitrary number of sub-frequency (including the odd-even numbers and decimals) design methods (including VHDL
SRT
- verilog code radix-2 SRT divider input [7:0]Dividend input [3:0]Divisor output [4:0]Quotient output [8:0]Remainder -verilog coderadix-2 SRT dividerinput [7:0] Dividend input [3:0] Divisor output [4:0] Quotient output [8:0] Remainde
divider
- 基于Verilog的除法器设计，可以直接在Q2里面运行哦~-Verilog-based design of the divider, which can be run directly in Q2 Oh ~
devider
- a divider design based on verilog language
dividers
- verilog格式的除法器，试过了，很好用，再也不要为触发器发愁了-Verilog format divider, tried, very good, and no longer for the flip-flop not to worry about the
divider
- a clock divider vhdl code
divider
- verilog divider hardware