搜索资源列表
xc9572_1
- xilinx xc9572 cpld 实现的伺服电机控制器，电机控制输出，和增量编码器读取。-Xilinx xc9572 cpld achieve servo motor controller, motor control output, Incremental encoder and the reader.
zhuanpan.rar
- 增量式光电编码器输出四分频脉冲计数，分别为A，B两路信号,Incremental optical encoder pulse count output frequency of a quarter, namely A, B two-way signal
coder_counter
- 增量式光电编码器计数器的FPGA实现程序,verilog3段式FSM,异步加载.-Incremental Optical Encoder counter program FPGA implementation, verilog3 struts FSM, asynchronous load.
SM2100
- 基于CPLD的增量式光电码盘SOPC使用手册-CPLD-based incremental photoelectric encoder SOPC Manual
VHDL
- PWM控制就是产生一定周期，占空比不同的方波信号，当占空比较大时，电机转速较高，否则电机转速较低。当采用FPGA产生PWM波形时，只需FPGA内部资源就可以实现，数字比较器的一端接设定值输出，另一端接线性递增计数器输出。当线性计数器的计数值小于设定值时输出低电平，当计数器大于设定值时输出高电平，这样就可通过改变设定值，产生占空比不同的方波信号，从而达到控制直流电机转速的目的。 直流电机控制电路主要由2部分组成，如图1所示： FPGA中PWM脉宽调制信号产生电路； &
quaddecoder_verilog_ise11.2_used_09042010
- Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descr ipted in the Constrained file quad.ucf. To use them, y
pld_encod11
- AHDL增量式光电码盘四倍细分后，自动计数转换成绝对数据-AHDL incremental photoelectric encoder segments four times, the automatic counting data into absolute
incremental
- 这是基于DE2平台的增量式编译实验,对初学者很具有参考价值-This is based on incremental compilation DE2 platform experiment, a very useful reference for beginners
work
- 增量式正交光电解码盘FPGA verilog-Incremental orthogonal optical disk FPGA verilog decoder
niosSDCARD
- This folder contains data for incremental compilation. The compiled_partitions sub-folder contains previous compilation results for each partition. contains previous compilation results for each partition.-As long as this folder is preserved,
xinhao
- 简易信号发生器，可输出三种波形，递增锯齿波发生器模块，正弦波发生器模块，方波发生器模块，波形选择器模块，vhdl-Simple signal generator can output three waveforms, incremental sawtooth generator module, the sine wave generator module, a square wave generator module, waveform selector module, vhdl
SEG
- 采用DE2 实现数码管递增 VERILOG-Using DE2 achieve the digital pipe incremental VERILOG
xinhaofashengqi
- 多功能信号发生器使用说明书 1.按键部分的使用 K1表示递增锯齿波、K2表示递减锯齿波、K3表示三角波、K4表示阶梯波、K5表示方波、K6表示正弦波、A表示整数部分幅度调节（步进值1V）、A.表示小数部分幅度调节（步进值0.1V）。最后两个按键留作以后升级使用。 2.拨码开关的使用 本次设计使用的是8位的拨码开关，第8位（FC）代表调频，拨通即可调频，第7位（ZANKONG）代表调整方波的占空比，拨通即可调占空比。开关拨通即相应的CPLD输入口为高电平。-Versa
inc_pid
- 基于FPGA的增量式PID设计方法，Matlab、Simulink， Xilinx Block set-Incremental PID FPGA-based design methodology
zengliangPID
- pid算法中的增量式pid类型算法，偏差计算模块的详细程序-Type pid algorithm of incremental pid algorithm, deviation calculation module of the program in detail
Descending-ramp
- 递减斜波是一种原理和递增斜波相似的波形，只需将递增斜波的循环加法计数换成1111 1111 1111～0000 0000 0000循环减法计数即可。-Harmonic is a descending ramp and incremental principle similar waveforms, simply incremented counts up the ramp into the cycle of ~ 1111 1111 1111 0000 0000 0000 cycle counti
DA
- 结合硬件描述语言与电路设计的DA转换器设计，实现了递增波，递减波，阶梯波，三角波等-Combined with hardware descr iption language and circuit design of the DA converter design, to achieve the incremental wave, decreasing wave, ladder wave, triangular wave, etc.
Xilinx的增量编译技术
- 增量编译技术，其基本原理就是根据前一次编译的结果，只重新编译部分修改过设计，其它部分则沿用前一次编译的结果，这样就可以缩短总体的编译时间(Incremental compilation technology, the basic principle is based on the results of the previous compilation, only re-editing part of the modified design, the other part is based on
ABencode
- FPGA实现增量式光栅尺正交脉冲解码，基于Verilog(FPGA realization of incremental grating ruler orthogonal pulse decoding, based on Verilog)
PID
- 利用Verilog语言实现PID增量式控制，输出占空比(Using Verilog language to realize PID incremental control and output duty cycle)