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Lab11
- 32bits FIFO with synchronizer. pass the synthesis using Synopsys tools-bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools
spi
- VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the \"master\" and the \"slave\". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits
Synthesizable_FIFO_verilog
- Synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth is
5bit-adder-subtracter
- 5 bits 的加法器與減法器合併電路之原始程式製作
multiplier
- 在MAXPLUSII下实现BOOTH算法，可以进行任意位K×K的乘法-BOOTH algorthim implemented in the MAXPLUSII environment, which can carry out arbitrary bits multiplication.
uart8.zip
- 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。,Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to sta
trunk-hdlc.rar
- 高级链路层协议的实现，vhdl，fpga,- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern
hdl-hw1-brent-kung-adder
- BRENT KUNG ADDER 4 bits
pwm_key
- 用fpga ep2c8Q208实现的按键可控PWM信号发生器 （按键加了消抖模块，PWM寄存器位宽为32位）-Achieved with the fpga ep2c8Q208 PWM control signal generator key (key plus the debounce module, PWM register bit width is 32 bits)
ram_16bit.rar
- RAM写入16位，读出16位,并且通过计数器控制ram可以实现读入多个数据,This ram can write 16bits and read 16 bits
UART
- 自己实用Verilog编写的UART程序，1位开始位，8位数据位，1位停止位，本测试程序配置完管脚后，实用串口大师发送数据，则返回数据为发送数据+1-Verilog prepared their own UART practical procedures to start a bit, 8 data bits, 1 stop bit, the test procedure End pin configuration, the utility serial Master to send data,
FPGA-VHDL-DDS
- 基于FPGA的DDS波形发生器--程序，如果需要产生输出不同的位数的波形，可以自行修改程序中的rom表中数据位数-FPGA-based waveform generator DDS- procedure, if the number of bits required to generate output of different waveforms in the program can modify data in the table the median rom
dds2_ok
- 利用LPM_ROM和HDL设计的一个DDS信号发生器，分辨率优于1HZ，ROM表长度8位，8位频率控制字。-HDL design using LPM_ROM and a DDS signal generator, the resolution is better than 1HZ, ROM table length 8 bits, 8-bit frequency control word.
16Point-FFT
- 16点FFT VHDL源程序，The xFFT16 fast Fourier transform (FFT) Core computes a 16-point complex FFT. The input data is a vector of 16 complex values represented as 16-bit 2’s complement numbers – 16-bits for each of the real and imaginary component of a
top_pnadd32
- 32位元浮点数加法器,用于以VHDL编写的32位元CPU-32 bits floating-point Add
SN7485
- his design is a comparator that compares consecutive bits a0...a3 with b0...b3
cpu_16bit
- design cpu 16 bits by verilog HDL.
16_bits_CPU_verilog_code
- 利用Verilog设计的16位CPU的设计案例-the example of 16 bits CPU using verilog
A-Two-bits-Counter-Using-VHDL
- 两位VHDL编译计数器的简单实现，并带有异步的复位功能。-A Brief Realization of Two-bits Counter, with an Asynchronous Reset Function
N-bits-by-M-bits
- 这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器-This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier