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vhdl程序例子
- vhdl程序源代码，包括Combinational Logic Counters Shift Registers Memory State Machines Registers Systems ADC and DAC Arithmetic等-VHDL source code, including Combinational Logic Counters Shift Registers State Machines Registers Memory S
unicntr
- 通用寄存器的部分代码 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY traffic IS PORT(clk,sm,sb:IN bit mr,my,mg,br,by,bg:OUT bit ) END traffic -part of the general purpose registers IEEE code LIBRARY USE traffic IEEE.STD_LOGIC_1164
spi
- VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the \"master\" and the \"slave\". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits
s_fifo
- 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench
i2c_S
- I2C Slave module The module contains N accessable Registers when in read Process, all Registers are read at a time when in write Process, only the addressed register are Writeable.
VHDL 语言例程集锦
- 包括很多有用的VHDL源代码，如下。文件为PDF格式，可以直接copy你想要的部分，然后粘贴到你自己的VHDL文件中。能帮你节省很多开发时间。 1.Combinational Logic 2.Counters 3.Shift Registers 4.Memory 5.State Machines 6.Registers 7.Systems 8.ADC and DAC 9.Arithmetic
VHDL
- 支持十条指令的微处理器 包括add sub mov mvi jmp jz in out sti lda微指令 支持8个寄存器 16位数据总线 地址总线 -Supports 10 microprocessor instructions, including add sub mov mvi jmp jz in out sti lda microinstruction registers support 8 data bus 16-bit address bus
multiplier-accumulator(vhdl)
- 用VHDL语言描述和实现乘法累加器设计,4位的被乘数X和4位的乘数Y输入后，暂存在寄存器4位的寄存器A和B中，寄存器A和B的输出首先相乘，得到8位乘积，该乘积再与8位寄存器C的输出相加，相加结果保存在寄存器C中。寄存器C的输出也是系统输出Z。(原创，里面有乘法部分和累加部分可以单独提出来，很好用) -With the VHDL language to describe the design and realization of multiplier-accumulator, four of
pwm-c
- 用VHDL编写的PWM控制程序，通过寄存器控制20余路PWM输出；qar是quartus的压缩包格式-VHDL prepared using PWM control procedures, through the registers to control more than 20 road PWM output qar is Quartus compressed packet format
DE2_VGA3
- The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow
unicntr
- 通用寄存器，可以双向计数存储，模式通过三位比特数据进行控制-General registers, can be bi-directional counting storage, mode of data through the three-bit control
dffasynchronous
- this ram both asynchronous and synchronous reset signals which is basic for any registers and basic memory element-this is ram both asynchronous and synchronous reset signals which is basic for any registers and basic memory element
VHDLprogram
- 含有各类寄存器，AD和DA转换器，各种算法，有限状态机，还些许组合逻辑电路设计代码-Containing various types of registers, AD and DA converters, a variety of algorithms, finite state machine, but also some combinational logic circuit design code
8-way-control-lantern
- 8路移存型彩灯题目要求两种花型，本次实验分别实现这两种花型，它的设计主要采用74194接成扭环形结构的移位寄存器来实现，整个电路主要由编码发生器、控制电路、脉冲发生器构成可以实现控制8个以上的彩灯，并且可以组成多种花型。 -8 subject lantern-type shift registers require two flower type, respectively, the experimental realization of the two flower types, it i
MAC_rd
- DM9000A读寄存器模块, verilog HDL-read DM9000A registers ， in verilog HDL
LatticeMico8_v3_0_Verilog
- The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice. Combining a full 18-bit wide instruction set with 16 or 32 General Purpose r
yetert
- This package includes 4-bit calculator designed in Xilinx FPGA 10 using VHDL. This calculator contains 3 registers, 1 ALU, 1 decoder and 1 FSM (finite state machine).
Design-of-general-purpose-registers-vhdl-language.
- 寄存器设计，以VHDL语言设计模拟一个通用寄存器。可供初学者学习。-Register is designed to simulate a VHDL language design general-purpose registers. For beginners to learn.
clock-synchronized-registers
- 一般来说，CPU的读写时钟会引入到PLD中，笔者利用CPU的读写时钟实现同步读写寄存器，提高设计的可靠性。因此这种建模方式是推荐的CPU读写PLD寄存器建模方式-In general, CPU clock will read and write the introduction to the PLD, the author uses the CPU to read and write clock synchronized read and write registers, improve des
Registers
- Registers behavioral,simulation and gate implementation code