搜索资源列表
test_uart
- uart VHDL code : include tx,rx,parity bit control
uart_tx_rx
- 该工程用verilog编写，已通过串口调试助手调试通过，接收模块采用8倍波特率采样数据，有较好的滤波功能，在PC上完成自发自收功能。-Verilog prepared by the project, has passed through the serial debug debugging assistant, receiving 8 times the baud rate module sampling data, a better filtering in the PC to complet
uart
- uart - veiloghdl rx, tx, baudrate-uart- veiloghdl rx, tx, baudrate
chipscope_Tx-Rx
- chipscope analysis of mini uart module including counter for spartan 3e
uart_top
- UART的verilog代码，tx，rx皆可-Verilog code of UART, tx, rx Jieke
uart_rx.fit
- uart core : uart rx fit
uart
- Verilog 编写全双工UART input clk, // 这个模块的主时钟 input rst, // 同步复位信号 input rx, // 串口接收端口 output tx, // 串口发射端口 input transmit, // 发送信号 input [7:0] tx_byte, // 发送的字节 output received, // 表明，已接受到一个字节 output [7:0] rx_
uart_rx
- UART RX spartan 3e starter kit
uart_rx
- 硬件描述语言设计的串口UART 接收源代码。-VerilogHDL UART RX RTL SOURCE CODE
UART
- URAT设计，系统包括五个模块，MCU模块，TX发送模块，RX接受模块，波特率产生模块，复位模块。-URAT design, the system consists of five modules, MCU module, TX transmit module, RX accept modules, baud rate generator module, reset module.
New-Folder-(2)
- UART communication on SPARTAN 6 it contains tx and rx
RX_ASYNC_for_module_UART
- Rx Async for module UART written in Verilog Libero Designer core generator.-Rx Async for module UART written in Verilog Libero Designer core generator.
RS_232_Test
- this file is a driver for rs-232 protocol. tx and rx. working for as uart protocol
Uart
- 使用verilog语言实现FPGA与计算机串口的通信，包括clk分频，uart顶层文件，rx，tx。使用verilog-FPGA serial port to communicate with the computer, including the speed choose, uart top file, rx, tx. Use Verilog
URAT-VHDL
- vhdl版本的uart收发程序，方便实用-uart vhdl rx/tx
uart2bus_latest
- uart IP, including rx,tx module,and FSM control,data paser logic. including: testbench-uart IP
uart
- 基于verilog的fpga串口通信,rx,tx.两根线(Basend on verilog fpga uart tong xin)
OTU_RXBLK
- cctv otu rx block source
uart_test
- verilog实现UART收发功能，硬件平台为spartan 6，软件平台为ise14.7(verilog implement UART rx and tx function)
uart_receiver
- Uart receiver VHDL code