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FPGAPROGRAMCHAPTER6
- FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节，然后把它接收回来。 -FPGA development board to write the Verilog code: function is from the client computer sends a byte, and then receive it back.
s7enable_send0x55_UART_9600
- 最简单的UART发送程序，vhdl编写，系统时钟40M，波特率9600，外Load有效（一个高脉冲）即向PC发送一个字节0X-UART to send the simplest procedures, vhdl prepared, the system clock 40M, baud rate 9600, outside the Load effective (a high-pulse) to the PC sends a byte 0X55
Priority_Encoder
- Unlike a multiplexer that selects one individual data input line and then sends that data to a single output line or switch, an Encoder takes all the data inputs one at a time and converts them to a single encoded output. Then, it is a multi-input da
Encoder_Using_Assign_Statement
- Encoder Using Assign Statements: Unlike a multiplexer that selects one individual data input line and then sends that data to a single output line or switch, an Encoder takes all the data inputs one at a time and converts them to a single encoded o
Tutorial_5
- 一个序列检测器的FPGA设计实验，通过LED灯显示，基于Spartan-3e开发板-The sequence detector will look for the input series “10010.” LED’s will show how much of the series has been detected and when the entire series has been entered an additional LED will come on. Circuit input
Counter-60
- In this example, counter 60 is implemented as part of the real time clock time electronic clocks. Done in the platform mentor Graphics and describes in the VHDL code. This counter has a role to the front edge of every 60 clock sends a signal followin
decrypt_controll
- controller for fast_aes128. Sends start and load pulses at a lower clock than main_clk.
EasyFPGA030-
- 用EasyFPGA030开发板来实现串口通信接口，通过电脑端发送相应的数据，可以控制板上的LED灯和特定端口电平的变化。 -With EasyFPGA030 development board to implement serial communication interface, through the computer sends the appropriate data, the control panel LED lamp and a specific port-level change
check_net_test
- 用来检查FPGA通过PHY发送数据时是否有掉帧的现象-FPGA is used to check whether the PHY sends the data out of the frame with the phenomenon of
I2C-
- 单个地址的读写 I2C总线的数据都是以字节(8位)的方式传送的，发送器件每发送一个字节之后，在时钟的第9个脉冲期间释放数据总线，由接收器发送一个ACK(把数据总线的电平拉低)来表示数据成功接收-The address of a single reading and writing the I2C bus of the data bytes (eight) way to transmit, send each device sends a byte after, the clock pulse 9
inout_test
- there are two madules,both of them contain an inout port,As module1 sends out data on its inout port,the inout port on second module would be an input,and vice versa
led_RS232
- 串口通信实例，单片机发送一帧数据，上位机接收，并点阵显示，模拟16*16LED点阵效果。-Examples of serial communication, microcontroller sends a frame data, the host computer receives, and dot matrix display, analog 16*16LED lattice effect.
jieshoufasong
- 实现FPGA和PC机之间的通信。PC机发送的数据可以通过FPGA显示在数码管上；FPGA通过按键发送的数据可以显示在PC机的串口调试助手上。-Communication between the FPGA and the PC. PC sends the data can be displayed through the FPGA digital tube FPGA through the button to send the data can be displayed on a PC seri
yibuchuanxingjiekou
- 能进行异步全双工串行通信的模块，该模块以固定的串行数据传送格式收发数据。每帧数据共10 位，其中1 位启动位，8 位数据位，1 位停止位。模块发送的数据由PC 端的串口调试助手接收，要求能发送数字和中文（一首古诗，在FPGA内采用ROM 的方式存储中文内码），并能进行切换。模块接收PC 端串口调试助手发送的16 进制数据，可按10 进制方式显示到LED 上。-Asynchronous full-duplex serial communications module can be performe
shumaguan
- ７段数码管测试：以动态扫描方式在８位数码管“同时”显示０--7 动态显示的方法是，按一定的频率轮流向各个数码管的COM端送出低电平，同时送出对应的数据给各段-7-segment digital tube test: dynamic scanning in eight digital tube "simultaneously" Showing 0- 7 Dynamic display method is to rotate at a certain frequency to each di
uart_verilog
- Verilog HDL语言编写的uart程序，在别人基础上改动和优化完成，quartus ii 10.0编译通过，可综合，板上仿真通过。将PC机发送的字符串发送回，可一次发送多个字符串。-Verilog HDL language uart program, in others on the basis of changes and optimization is complete, quartus ii 10.0 compiler, integrated, on-board through si
uartfifo
- 一个基于verilog的fifo的例子，由数据产生模块产生数据传到fifo中，然后同过发送模块将数据发到上位机上。-One based on the fifo verilog example, by the data generation module generates data to the fifo, and then sent over the same module sends data to the host computer.
EX7
- 一个基于verilog的串口接收发送模块，可与上位机通信。-One based on the serial receiver sends verilog module can communicate with the host computer.
uart_fifo
- 带fifo的串口通信verilog设计，该设计为学习uart所用，完成PC端发送至fpga后fpga原数据返回，支持长字符串。-Serial communication with fifo verilog design, which is used to learn uart complete PC sends data back to the original post fpga fpga, support long strings.
FPGA_Project_Files
- 此例为FPGA发送数据包到pci9054，用到fifo模块，还有sram模块，比较复杂。应用在pci9054与fpga通讯-This example sends the packet to the FPGA pci9054, use fifo module, as well as sram module, is more complex. Application pci9054 communication with fpga