这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流水线和Verilog的朋友共享。,This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! T

vhdl comprator and miley version that can simulate ans synthesis in all aoftwares like modelsim and quartus and ise

用VHDL实现的RS（63,45）编码器，已经用ISE和questasim编译仿真通过。对45个信息位进行编码。-VHDL implementation of the RS (63,45) encoder has been compiled with the ISE and questasim through simulation. Of 45 information bits are encoded.

this is a clock generator program by using concurrent language verilog hdl with xilinx ise.