搜索资源列表
usb1.1phy
- USB 1.1 PHY的代码，verilog语言 USB 1.1 PHY的代码，verilog语言-USB 1.1 PHY code, verilog language USB 1.1 PHY code, verilog language
sata_device_model
- sata_device_model,对做硬盘控制器的朋友有帮助-sata_device_model, to make the hard disk controller has a friend help
mdio
- MDIO verilog RTL代码，SOC可以通过MDIO接口来访问外部PHY等慢速外设-MDIO verilog RTL code
mdio
- cpu与phy通信，让cpu能读写phy芯片，实现通信-cpu communication with phy
MAC
- Verilog code for MAC
smii_latest.tar
- SMII接口的mac控制器，通过测试。使用verilog语言！-The Serial Media Independent Interface, SMMI, is a low pin count version of the MII normally used between ethernet MAC and PHY. The Serial Media Independent Interface (SMII) is designed to satisfy the following r
USB_IP-CORE-design
- USB2.0的IP核，需要添加额外的PHY模块，使用Verilog语言编写-USB2.0 IP core, you need to add additional PHY module, using the Verilog language
MII
- 以太网MII芯片配置接口的VHDL设计，配置PHY芯片的模块设计-Ethernet MII chip configuration interface VHDL design, configuration PHY chip module design
MDIO
- 网络PHY88E1111的 寄存器 通讯协议的 verilog描述 能实现 lookback 能读出PHY的资料-The register communication protocol Verilog descr iption of the network PHY88E1111 lookback can read the PHY data
USB_fpga
- FPGA与USB PHY芯片Cy7c68013A通信的程序，Verilog语言-FPGA and USB PHY chip Cy7c68013A communication procedures, Verilog language
K7_1M
- 用Verilog语言实现的以太网驱程，可最多实现8个以太网，外加PHY后，可实现ping操作-Ethernet drive-by Verilog language can achieve up to eight Ethernet, plus after PHY, can achieve a ping
sata_phy_latest.tar
- 用verilog写成的sata2的phy物理层，可应用与sata2的控制层下层接口！-Phy written by verilog sata2 the physical layer, the lower layer can be applied to the interface control layer and sata2!
SRIO-phy-code
- SRIO接口物理层的实现代码，非常复杂，完全自己用verilog编写，支持5G速率，可以作为开发参考-SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development
udp_send1
- 基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output
help_lib
- 1.JESD204B协议 2.Xilinx的JESD204B phy 核手册 3.Xilinx的JESD204B rx_tx 核手册7.1 4.Xilinx的JESD204B rx_tx 核手册7.2 5.verilog实现串口发送(1.JESD204B protocol 2.Xilinx JESD204B PHY core manual 3.Xilinx JESD204B rx_tx core manual 7.1 4.Xilinx JESD204B rx_tx core man
14_ethernet_test
- 千兆网学习代码 ISE，状态机实现数据打包，基于PHY芯片实现数据传输(ethernet communication sample with verilog,state machine)
DBSTAR_RGMII
- Verilog实现的RGMII和GMII接口转接，适合适配不同PHY芯片接口使用(Verilog implementation of RGMII and GMII interface transfer)
utmi
- 介绍USB PHY接口中的UTMI接口， 对使用Verilog进行USB接口编程具有帮助。(This paper introduces UTMI interface in USB PHY interface. It is helpful for programming USB interface with Verilog.)
802.11a PHY 代码
- 802.11a 物理层代码，采用verilog编写FPGA设计