资源列表
xapp336_8b10b
- 可编程器件大厂Xilinx提供的高速多状态编码8b_10b编码器，可直接使用在Xilinx公司器件的设计上-Xilinx programmable device manufacturers to provide high-speed multi-state coding 8b_10b encoder, direct access to the Xilinx devices on the design
USB 2.0 IP Core
- USB20的IP CORE,可以直接用在SOPC下，自动完成全部的枚举，只需修改枚举参数即可！-USB20 IP CORE, can be directly used in SOPC, automatically complete the enumeration. only a modification of enumerated parameters can be!
异步FIFO存储器的控制设计
- 异步FIFO控制器的设计 主要用于异步先进先出控制器的设计。 所用语言Verilog HDL.-asynchronous FIFO controller design for the main asynchronous FIFO controller design. The language used Verilog HDL.
用一位全加器组成四位全加器
- 用一位全加器组成四位全加器. 所用语言是Verilog HDL. 主要用在加法器的设计中。-All-Canadian with a composed four-adder. The language used is the Verilog HDL. In addition main The design.
crc_verilog_xilinx
- CRC校验码，用于对数据流进行crc校验。 主要有CRC_16,CRC_8,CRC_32校验。 所用语言为Verilog HDL.-CRC code for the data flow crc check. Main CRC_16, CRC_8, CRC_32 check. The language used for Verilog HDL.
等精度频率计
- 使用vhdl语言写的fpga的应用程序，使献策内容为等精度频率计-use of the VHDL language they simply write the application procedures so that such ideas as to accuracy Cymometer
ADD_SUB
- 11,13,16位超前进位加法器的Verilog HDL源代码。-11,13,16-CLA for the Verilog HDL source code.
用VHDL实现布斯算法
- 这个例子是讲述用VHDL实现布斯算法，应该有点用，是我的研究生师哥给我的。-this case is about the use of VHDL Booth algorithm, should use a bit of my graduate students Shige to me.
conv_code
- 用VHDL实现卷积码编码，该码为（2.1.3）型卷积码。-using VHDL Convolutional coding, the code (2.1.3) - Convolutional Codes.
Modelsim上机指导
- 一本详细讲解有关modelsim操作的教程,非常适合初学者.-a modelsim explain in detail the operation of the guides, very suitable for beginners.
pinlvji
- 本频率计具有测周、测频、测量占空比等基本功能，能自动换档，误差为1%-the frequency meter is measuring weeks, frequency measurement, measuring the ratio of the basic functions can automatically shift error of 1%
cal_verilog
- 计算器芯片的verilog实现代码！ 时序仿真成功-calculator chips to achieve the Verilog code! Timing simulation success