资源列表
key_counter
- 4X4 KEYPAD 的输入位数计数器，可以自己定义输入的位数-4x4 KEYPAD median counter input, input their own definition of the median
sdr sdram controller
- ALTERA sdram vhdl与verilog参考设计-Altera SDRAM VHDL and Verilog reference design
air_conditioner
- 空调温控电路有限状态自动机， 有ＴＥＭＰ＿ＨＩＧＨ和ＴＥＭＰ＿ＬＯＷ 分别与传感器相连用语检测室内温度．-air-conditioning temperature control circuit finite state automaton, and TEMP_LOW TEMP_HIGH with sensors connected to the indoor temperature detection terminology.
DSP 应用与实例 附TMS320LF2407(EVM) DSK 原理图
- DSP 应用与实例 附TMS320LF2407(EVM) DSK 原理图，谢谢大家！-DSP applications with examples : TMS320LF2407 (EVM) DSK schematics, Thank you!
ispLEVER培训教程
- ispLEVER是LATTICE的CPLD、FPGA继承开发环境-ispLEVER CPLD, FPGA development environment succession
control step motor
- 步进电机控制，控制器,控制电机的VHDL源程序-stepper motor control, controllers, motor control VHDL source
Verilog DHL数字钟
- 用Verilog DHL语言编写的一个数字钟程序,除了基本计数,还具有校时,闹钟功能-Verilog language used in the preparation of a digital clock procedures, in addition to the basic count, but also with school, an alarm clock
VHDL 的实例程序，共44个
- 经典VHDL 的实例程序，共44个！要下载的尽快-classic examples of VHDL, with a total of 44! To download as soon as possible
抢答器
- 扳动定义为“开始”（即enable）的开关后，一排指示灯变亮，之后抢答开始，有4个扳动开关代表4个抢答器，数码管将显示出最先被扳动的开关的序号，同时发出声音，表示抢答成功。若未按“开始”前，有任意开关被扳动，则数码管显示被扳动开关的序号，并发出另一种声音，表示有人抢答。-reached for the definition of "start" (enable) the switch, a row of bright lights changed, after Respond
8位加法器
- 8位加法器的原代码,主要内容下载看了就知道-Adder eight of the original code, read the main content downloaded know
ddsVHDL
- 基于VHDL的DDS设计，在QUTURS2zhon仿真通过-based on the DDS VHDL design and simulation through the QUTURS2zhon
verilog实例
- 一些很实用的verilog源程序，是初学者的好棒手，希望能给需要的人一点帮助，请支持一下。-some very practical Verilog source is the beginners excellent hands, in hopes of giving those who need a bit of help, please support what.