资源列表
Verilog-float-mutiplier
- 32位浮点型乘法器，和开方器,很有用的一种，就是认真读懂-32 float mutiplier
usb_phy.tar
- Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check f
ssram
- 同步静态RAM读写程序，可用作模块，已通过ISE12.4验证-Synchronous Static RAM read and write procedures, can be used as modules, have been verified by ISE12.4
caiheng
- 利用Verilog实现32位浮点数的乘法,并且已通过验证.-Using Verilog to achieve 32-bit floating point multiplication, and has been verified.
dpll
- dpll的verilog代码，完成数字锁相。用于时钟对准，位同步。-dpll the verilog code to complete the digital phase-locked. Alignment for the clock, bit synchronization.
SHFRT4_1
- 四位串入并出移位寄存器,实现串并转换,已通过时序验证-Four series in and out of shift register, to achieve string and conversion, has passed the timing verification
CY7C68013_DEMO
- cy7c68013原理图和程序 实现fpga和68013通信程序代码-Cy7c68013 principle chart and procedures To realize the fpga and 68013 communication program code
dac
- 基于FPGA实现对DA芯片的控制，以及时序的编写-FPGA control to DA chip
divider
- 移位快速除法器，通过一次移4位试商实现快速除法功能，较普通减除法器有及其巨大的效率提升-Divider rapid shift by a shift to four test functions of rapid division, as compared with ordinary objects have less efficiency and its huge
FIFO-verilog
- 两种异步FIFO设计以及源代码（Verilog）-Two asynchronous FIFO design and source code (Verilog)
VHDL100
- 一套不错的VHDL例子，附带清华大学自主研制的仿真器，仿真结果都有的，希望给您提供很方便-VHDL a good example of self-developed with Tsinghua University, simulator, simulation results are, I hope to provide you with easy
verilogsram
- FPGA开发板上的VerilogHDL编写的SRAM读写试验程序, 包括介绍文档, Verilog源码, 在Quartus II 8.1环境下测试通过-FPGA development board SRAM VerilogHDL prepared to read and write test procedures, including the descr iption document, Verilog source code, the Quartus II 8.1 environment te