资源列表
mutl16 实现16位移位乘法和除法
- 实现16位移位,可以实现乘法和除法。满足设计要求,实现代码简短,用verilog完成方便,容易操作。-Achieve 16-bit shift, multiplication and division can be achieved. Meet the design requirements to achieve a short code, complete with verilog convenient, easy to operate.
i2c总线的vhdl实现和vxworks的文件系统.rar
- i2c总线的vhdl实现和vxworks的文件系统,i2c bus VHDL realization and VxWorks file system
MiniStep.rar
- XC95144步进电机驱动器源码,采用verilog vhdl开发,个人原创,XC95144 stepper motor drive source, using verilog vhdl development, personal originality
FPGACOM.rar
- FPGA编程实现串口通信,源代码全。包括仿真程序。,FPGA programming serial communications, the entire source code. Including the simulation program.
Sobel.rar
- 这是一个用VHDL实现SOBEL算子进行图像边缘算法的实现,This is a realization by VHDL Sobel edge operator algorithm
accumulator.rar
- 实现累加器的verilog源码,广泛应用在通信电路设计中,The realization of accumulator Verilog source, widely used in communication circuit design
multiply2.rar
- 18bit的booth乘法器 采用booth2编码 Wallace压缩树 以及超前进位结合进位选择的36bit高性能加法器,18bit multipliers used booth2 the booth encoding and Wallace tree compression-ahead into the location choice of high-performance 36bit adder
tAtan2Cordic.rar
- 是codic算法实现atan的C程序,包括定点和浮点程序,已经通过验证。,Atan is codic algorithm of C procedures, including fixed-point and floating-point procedures, has been validated.
vcs_simulation_mannual(Edition
- VCS-verilog compiled simulator是synopsys公司的产品.其仿真速度相当快,而且支持多种调用方式.该文档是一个不错的使用指南.,VCS-verilog compiled simulator is the Synopsys company s products. Its simulation at a fairly rapid pace, and support multiple call mode. This document is a good guide.
oc_i2c_master.rar
- 这是一个I2C的IP。直接拷到altera公司的相应软件的目录下,即可应用。,This is an I2C of IP. Kaodao altera directly corresponding software company directory, can be applied.
usb11.rar
- 基于verilog HDL的一个USB 1.1的IP 核,内有详细文档说明。,Verilog HDL based on a USB 1.1 of the IP core, which has detailed documentation.
ISA.rar
- pc104代码,这是本人调通过的。标准ISA通信接口,用VHDL编写,pc104 code, This is my tune adopted. ISA standard communication interface, using VHDL prepared