资源列表
DDRSDRAM
- DDR SDRAM的veilog hdl程序，经过验证 效果不错-DDR SDRAM' s veilog hdl procedures, good results verified
dds
- 本程序代码为DDS的程序代码。采用VHDL语言设计。可以直接仿真实现，-The program code of the program code for the DDS. Design using VHDL language. Simulation can be achieved,
fft_rtl
- rtl实现的fft变换，经硬件测试其功能与altera的fftip核相近-fft transform based on rtl design
CPU
- 实现简单CPU功能的源码，可以实现加减乘除和移位功能，VHDL代码，程序运行在MAX PULS和Quartua上。-The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The Altera’s Maxplus Ⅱ EDA tool is recommended
c54x_verilog
- TI 的TMS320C54X的DSP的芯片软核verilog源代码，可以帮助初学者深入了解该系列DSP片内资源核结构，值得参考！-TMS320C54X of TI' s DSP chip soft-core verilog source code, can help beginners a better picture of the family of DSP-chip resources, nuclear structure, it is also useful!
27796704802_11a
- 以FPGA实现802.11MAC协议,对新手很有帮助-FPGA realization of an agreement to 802.11MAC
encoder
- 编码器信号处理 经过倍频器进行四倍频 后 同时完成鉴相 计数-the encoder single program
olb-0.5r1
- open source lattice boltzma-open source lattice boltzmann
21controlFPGA
- 21control的系列FPGA开发板原理图-21control series FPGA development board schematics
Elevator
- 基于FPGA的6层电梯控制器，使用VHDL编程，用quartus ii进行仿真模拟-Elevator Controller
DE2_NIOS_CharLCD
- nios ii在DE2上实现LCD动态显示，运行成功-nios ii in DE2 to achieve LCD dynamic display, running a successful
vga
- vga接口的源码测试程序、Verilog语言编写-vga