资源列表
PCMencoder
- 根据PCM编码特点，利用VHDL来设计出采编器；本设计为码率2Mbs，子长为8位，帧长100位。-According to the characteristics of PCM coding，here we use VHDL to design a editing device。
barrel_shifter
- VHDL实现的桶型移位器，能在一个时钟周期实现对数据的（0－12位）算术右移-VHDL implementation of a barrel—shifter, able to achieve at one clock cycle of data (0-12 bit) Arithmetic Shift Right
NANDFLASH
- 用VHDL开发的NANDFLASH的读写程序,给出 NANDFLASH的时序正确的读写-NANDFLASH developed using VHDL to read and write the procedures, timing NANDFLASH give the correct reading and writing
jpeg.tar
- This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288). Image resolution is no
XC4VLX40_FGPA
- 使用xinlinx的XC4VLX40_FGPA编写的串口程序-XC4VLX40_FGPA of xinlinx, the seiral communication program
FPGA-PS2-interface
- FPGA的PS2口接口程序，可识别PS2口键盘的输入-FPGA-PS2 port interface program to identify the mouth PS2 keyboard input
Avt3S400A_Eval_MB_parallel_flash_v10_1_01
- FPGA 并行NOR FLash的操作相关，很实用的，基于Xilinx SPartan-3 -FPGA parallel operation of NOR FLash related, it is practical, based on the Xilinx SPartan-3
traffic
- vhdl实现的交通灯，分为主次干道，分别计时-vhdl traffic light
vhdldds0000
- 采用fpga的hdl语言实现dds的信号发生器的设计，性能与传统相比明显提高。-Hdl language using FPGA implementation of the signal generator dds design, performance markedly improved compared with the traditional.
PCI_VHDL
- pci控制器的vhdl代码-pci vhdl
LVDS_DDR_List_FPGA2
- FPGA芯片与ADI公司的AD9779之间的通信，总共有四个通道，68对LVDS,采样时钟是122.88MHz-FPGA chips ADI' s AD9779 and communication between, a total of four channels, 68 pairs of LVDS, the sampling clock is 122.88MHz
I2C_SLAVE
- I2C_SLAVER FPGA 源码 已经验证-I2C_SLAVER FPGA