资源列表
xhdl_4.1.4_demo_patch
- this is X-HDL Crack. support xhdl_4.1.4
fpga1244131245d
- 基于FPGA的FIR数字滤波器的设计与实现。滤波器设计参数可实现17阶和32阶线性相位FIR滤波器-FPGA-based FIR digital filter design and implementation. Filter design parameters can be achieved on 17 order and 32 order linear phase FIR filter
program
- 1/100s计时器的FPGA实现，本设计的计时器能实现显示最长计时时间为1分59.99秒，且精度大于1/100s，计时器能显示1/100s的时间.-1/100s timer FPGA, the design of the timer to achieve the longest time show time of 1 minutes, 59.99 seconds, and the precision is greater than 1/100s, 1/100s timer can display
Clocking-resources-Spartan-6
- CLOCK RESOURCES FOR SPARTAN 6 LX150T.
fpga
- quartus 难得一见的中文教程，fpga必读-quartus rare Chinese tutorial, fpga Required
NIOS-IP
- NIOS外围IP使用指南,NIOS外围IP使用指南，NIOS外围IP使用指南-NIOS peripheral IP Guide
ad-ram
- ad采样 通过fpga 传输给ram-ad fpga ram verilog
LCD_CLOCK
- 用1602液晶显示的数字电子钟，并且可以用按键开关调整时间，日期，星期。-1602 LCD display with digital electronic clock, and the key switch can be used to adjust the time, date, week.
vhdl
- 用VHDL语言实现的二进制到BCD码和格雷码的转换，程序通读性比较好。-VHDL language with the binary code and Gray code to BCD conversion, the program read through is better.
DS-Verilog
- ad 采集 串行ADtlv2543和DATLV5618的接口程序 -ad
dac5687_interface
- verilog语言编写的dac5687的接口程序，串行模式控制。-written dac5687 verilog interface program, serial mode control.
fft_2011_3_23(COMPLETE-FFT1024)
- VERILOG FFT IP核调用，以及其控制文件-VERILOG FFT IP core call, as well as its control file