资源列表
state_machine
- 基于FPGA用VHDL编写的状态机控制步进电机.-Prepared by the state machine control VERILOG stepper motor.
VGA
- FPGA实现VGA显示RGB彩条信号-FPGA to achieve VGA display RGB color bar signal ...
STATE_MECHINE
- FPGA 状态机控制步进电机..verilog-FPGA state machine controlled stepper motor .. verilog
verilog
- 介绍了一种硬件控制的自动数据采集系统的设计方法，包括数字系统自顶向下 (1DP—DOwN)的设计思路，Vernog}Ⅱ)L对系统硬件的描述和状态机的设计-Introduced a hardware-controlled automated data acquisition system design, including digital systems from top to bottom (1DP-DOwN) design ideas, Vernog} Ⅱ) L of the system
12
- Verilog HDL应用程序设计实例精讲源码-Verilog HDL design example application source code Jingjiang
msp430_i2c_uart
- msp430单片机的IIC 协议和UART协议，很好用的，都测试过哦-msp430 microcontroller and the UART protocol IIC protocol, well used, are tested oh
actel_FPGA_example_source
- actel中的FIFO的使用的示例代码，对于使用actel环境的初学者有一定的帮助。-actel the use of FIFO in the sample code for beginners to use actel environment will certainly help.
quartus-and-modelsim-for-OFDM
- 关于quartus与modelsim 仿真-about quartus and modelsim simulator
NIOS-II-AD-data
- 在NIOS-II 系统中AD 数据采集接口的设计与实现-NIOS-II system in the AD Data Acquisition Interface Design and Implementation
X-HDL
- 一款可以在verilog和VHDL之间互换的工具，经测试，暂无bug-A verilog and VHDL can be exchanged between the tools, tested, no bug
pwm
- 基于FPGA的PWM波的产生，通过计数的方法实现-FPGA-based generation of PWM wave
uart_vhdl_verilog
- 串口FPGA的实现源码，VHDL和Verlog两种语言源代码。-UART FPGA implementation source code, VHDL and Verlog two languages source code .