资源列表
unsig_altmult_accum
- 无符号型的基于累加器的乘法器，代码比较简单-unsigned altmultiplex accumultor
CCD_CPLD
- 内部资料，CCD探头采集时序发生器，基于CPLD用VHDL编写，是学习CPLD和VHDL在实际工业应用中的实际案例。-Internal information, medical collection probe CCD Timing Generator, based on the CPLD using VHDL, CPLD and VHDL to learn practical industrial applications in the real case.
FPGA_DDS
- FPGA中实现信号发生器,即DDS,代码简洁,精练,非常适合学习,已经经过验证.-The FPGA signal generator, or DDS, the code simple, concise, very suitable for learning, has been verified.
adda
- fpga作为ad与da的桥梁，实现快速模数，数模转换。-fpga as ad and da bridge, fast analog to digital, digital to analog conversion.
DAC-use-verilog
- 用verilog写的TLV5620芯片的DAC转换代码，核心文件dac.v，能进行实现，不仅仅是行为级描述-Written with verilog conversion code TLV5620 DAC chip, the core file dac.v, can be achieved, not just behavioral descr iption
Computer-Organization-experiment
- 上海交大计算机组成实验源代码 in verilog-computer organization experimentation source code
error-detection-device
- 使用Verilog语言编程，在Quartus ii 上实现的误码检测装置，并通过单片机将误码结果显示在LCD上。本代码具有一定的工程实践价值。-Using the Verilog language programming, implemented on the Quartus ii error detection device, and the result of errors by the microcontroller on the LCD display. The code has som
A-Memristor-SPICE-Model
- 一篇讲述如何在pspice软件中仿真忆阻器（memristor）替代蔡氏混沌电路中的非线性电阻进而观察研究混沌相图的文献-How about a software simulator pspice memristor (memristor) alternative Chua' s chaotic circuit chaotic nonlinear resistance and then observe the phase diagram of the literature
FIFOED_UART
- CAL_UART核verilog源码，带FIFO，FIFO深度可设置。-fifoed uart ip core. cal_uart.
CRC-8
- VHDL code for CRC-8 computing using 32 bit input (parallel)
yuanchengxu
- 基于Verilog HDL的通信系统设计-Design of communication system based on Verilog HDL
rt_32bit
- 通过Verilog实现的基于FPGA实现429总线格式转换接收程序-FPGA code for receive 429 message