资源列表
11_temperature
- verilog 语言实现的温度计。 FPGA 基本教程-a temperaturer basied on verilog .
RScoder
- 基于FPGA的RS编码器设计，verilog hdl语言。-RS encoder FPGA-based design, verilog hdl language.
dso
- 用FPGA设计的数字示波器，有详细的设计过程、论文和硬件原理图-Digital oscilloscope with the FPGA design, detailed design process, paper and hardware schematics
dtmf
- dtmf 8880 tx phone ca-dtmf 8880 tx phone call
MSB_search_verilog
- 使用Verilog实现16位数据最高有效位的查找-use verilog to search msb of 16 bits data
s25fl040a
- ST S25FL040 Sefial Flash Verilog Model
design-of-CAN-based-on-VHDL
- 基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计，实现其功能，并且能够在FPGA开发平台Quartos上通过仿真验证，证明其正确性-Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the C
JPEG
- JPEG解码(Verilog)源码，详细，高效。-JPEG decoding (Verilog)
AMI
- 在ISE软件环境下，用Verilog HDL语言实现通信中的AMI码的编码和译码，并有仿真波形。-In the ISE software environment, using Verilog HDL language for communication in the AMI code encoding and decoding, and a simulation waveform.
cdma
- 使用verilog在QII系统中开发的一个简单的4用户CDMA系统。-In QII system using verilog developed a simple four-user CDMA system.
4bit-adder_verilog
- 4位全加法器的modelsim工程带testbench-Four full-adder modelsim project with testbench
mult
- 4级流水乘法器，本文利用FPGA完成了基于半加器、全加器、进位保留加法器的4比特流水乘法器的设计，编写VHDL程序完成了乘法器的功能设计，并通过Modelsim进行了仿真验证。-Four water multipliers, this paper complete FPGA-based half adder, full adder, carry-save adder 4 bit pipeline multiplier design, write VHDL program to complete