资源列表
viterbi-ip-core-using-mothed
- FPGA的Viterbi译码器IP 核的使用说明，简单方便，一目了然。还能进行tcm译码，功能强大呀-Instructions for use of the FPGA Viterbi decoder IP core, easy glance. Can tcm decoding powerful!
juanji1
- 本程序是在Xilinx ISE上编写的，它完成（2,1,6）卷积码的编码工作。里面有源程序和用以仿真的测试文件-The program is written on Xilinx ISE, it completed the (2,1,6) convolutional code encoding. Source and for the simulation of the test file inside
juanji2
- 本程序是在Xilinx ISE上编写的，它完成（2,1,6）卷积码的译码工作。里面有源程序和用以仿真的测试文件-The program is written on Xilinx ISE, it completed (2,1,6) convolutional code decoding. Source and for the simulation of the test file inside
AD2S80
- 轴角转换芯片AD2SBOA的顺序代码，将角度信息输入到FPGA并精粗通道数据整合-Code of the the angle Converter chip AD2SBOA the order, the angle information input to the FPGA and to roughage channel data integration
oob_control
- sata协议物理层的OOB带外信号控制实现的VHDL代码-the sata protocol physical layer OOB band signal control VHDL code
sgmii_latest.tar
- This core implements Physical Coding Sublayer of 1000BaseX transmission (IEEE 802.3 Clause36 and 37). This core can also be used for SGMII interface as this interface leverages 1000BaseX PCS. The differences between the 2 protocols are Link-timer and
tanchishe
- verilog编写的贪吃蛇小游戏，能够在vga上显示，可以通过sp3键盘控制蛇的运动，吃食物-verilog prepared by the Snake game, vga on display by sp3 keyboard to control the movement of the snake to eat the food
ssram_Controler
- DE2-70开发板上的SSRAM的读取数据控制器，通过拨码可以实现读取数据。-DE2-70 development board SSRAM read data controller, through DIP can read data.
FPU
- 32位单精度浮点运算单元,遵从IEEE 754标准，持浮点加、减、乘、除等运算。-32-bit single-precision floating-point unit；comply with the IEEE 754 standard；support floating-point add, subtract, multiply operations.
cpld_ads7844_50M(9-24)
- 用ads7844采集数据，用cpld做时序控制，通过串口观察和记录采集结果，用verilog编写，通过开发板验证-Collected data using ads7844 timing control with cpld verilog prepared by the serial observe and record collection results through the development board verification
FPGA_IIC
- 这是我编写的FPGA控制IIC的程序，用来配置型号为24C02的EEPROM，已经通过验证。-This is my own Verilog HDL program for IIC control, it can configure the EEPROM named 24C02, and the program have been tested.
DE2_115_Default
- D2-115学习源码，功能配置，音频功能，LCD控制，视频同步产生器-Learning source D2-115, the functional configuration of the audio function, LCD control, video sync generator