资源列表
uart_trans
- 使用Verilog语言编写的多字节串口发送程序，可以同时发送56个字节。-Multi-byte serial port to send a program using Verilog language, you can also send 56 bytes.
PWM
- 基于FPGA的占空比可调以及频率可调的PWM波发生器的设计实现-FPGA-adjustable duty cycle and frequency adjustable PWM waveform generator-based design implementation
NewEthernet_06_03_2
- 用XILINX公司FPGA的嵌入式集成开发平台开发的千兆以太网的完整实现代码-Code with the integrity of the integrated development platform developed by XILINX FPGA-embedded Gigabit Ethernet
NIOS-II-raw-uart-program
- 基于NIOS II 的串口编程，从原理到程序都有介绍。-NIOS II based on the serial programming, from principle to the program are introduced.
pinlvji
- 这是一个简易数字频率计的源代码文件，基于DE-2 70，50MHz分频，四位十进制显示-This is a simple digital frequency meter source code files, based on DE-2 70,50 MHz sub-band, four decimal
music_player
- 用Verilog语言在FPGA上实现了音乐播放这一功能。预先将音乐《北京欢迎你》转换保存到FPGA的ROM中，由设计的音乐播放器按时序读出数据，予以播放。-Using Verilog language in FPGA realize the function of playing music.The music of "welcome to Beijing" was transformed and saved in FPGA ROM, the data was read by music pl
trivium
- trivium密码算法的 verilog 实现 测试正确-trivium password algorithm verilog test correct
Multiplier
- 一个乘法器的FPGA设计代码 Multiplier-fpga Multiplier
SPI_Master
- 此代码是SPI接口的Master的Verilog源代码，经上板测试是没有问题的，请大家放心使用-This code SPI Interface Master of Verilog source code, there is no problem on board test, please rest assured to use
responder
- 实现四路抢答器功能，主持人可以控制抢答开始，也可以将各个抢答器清零-Responder function to achieve four-way, the host can control the answer in the beginning, you can also clear the various Responder
altera_fft
- verilog实际例子，非常适合初学者学习-verilog practical examples, very suitable for beginners to learn
PipelineSim
- 用verilog编写的简单流水线CPU，指令集根据DLX指令集修改而来。只支持定点操作.-Verilog prepared by the simple lines with a CPU, instruction set modified from under the DLX instruction set. Supports only fixed-point operation.