资源列表
ad5764
- 数模转换器AD5764的Verilog HDL源程序，已在项目中验证了其可行。-DAC AD5764 Verilog HDL source code, and have verified its feasibility in the project.
code
- 基于FPGA的乘法器译码器程序，非常适合初级菜鸟学习使用入门程序，欢迎大家下载学习-FPGA multiplier based procedures, very suitable for learning to use primary rookie entry procedures, are welcome to download the learning
SP_SCH(Executable)
- 调度器一般包括SP、RR、WFQ等，SP调度指的是绝对高优先级调度，此种调度不带权重概念，按照优先级进行调度。四个按键作为端口有效指示，2个LED发光二极管指示此时调度的端口号，可以按下KEY3按键，按下按键代表当前按键输入无效，然后观测LED，没有按下的时候LED1 LED0都发光，按下KEY3按键的时候LED1发光 LED0不发光，代表此时调度端口为2，不按下时候代表调度端口为3。 -The scheduler typically include SP, RR, WFQ, etc., SP
AD80305
- 一种基于xilinx FPGA S6,verilog 实现AD80305输入输出接口配置，可参考-Based xilinx FPGA S6, verilog realize AD80305 input and output interface configuration, refer to
data_switch
- verilog 实现15bit数据与176bit数据间的相互转换，可根据此代码作一定的修改，可以实现其他位宽数据的转换-verilog to achieve mutual conversion between 15bit data with 176bit data can make certain changes based on this code, you can achieve the conversion of other bit-wide data
猜數字，終極密碼
- verilog code 可以控制玩家數目，及遊戲模式(有兩種:猜數字 + 終極密碼) 最後結果會顯示出排名及分數
RR_SCH(Executable)
- FPGA VERILOG调度器一般包括SP、RR、WRR、WFQ等，RR调度指的是轮询调度，此种调度不带权重概念，均匀轮询进行调度。-FPGA VERILOG The scheduler typically include SP, RR, WRR, WFQ, etc., RR refers to the round robin scheduling, dispatching without the weight of such concepts, even polling scheduling.
TCAM
- FPGA VERILOG TCAM (ternary content addressable memory)是一种三态内容寻址存储器，主要用于快速查找ACL、路由等表项。-FPGA VERILOG TCAM (ternary content addressable memory) is a ternary content addressable memory, mainly used to quickly find ACL, routing entries.
mvb_altera_may-02
- altera mvb fpga sopc 设计参考文档，有一定价值-mvb fpga sopc Design scheme
1553-EncoderDecoder---Documentation
- 1553b编解码参考设计 verilog 收发-1553b encoder decoder
Verilog_add_div_multi_exp
- 使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数，迭代次数（可设置）决定了精度。-Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.
FPGA 正交编码 verilog
- 用Verilog写的2倍频率正交编码的仿真测试程序，仿真波形已经调出