资源列表
audio_fft_vga
- 代码使用Verilog HDL实现了使用WM8731对音频进行采样，并且使用ALTERA FPGA实现了频谱计算（FFT），在VGA上显示频谱。-Achieved using the Verilog HDL code using WM8731 audio sampling, and use ALTERA FPGA to achieve the calculated spectrum (FFT), shows the spectrum on VGA.
fpga_fmsc
- 本代码在FPGA上实现了与STM32单片机的FSMC总线通信的时序代码，在ALTERA FPGA上得到验证。-The code on the FPGA to achieve with the STM32 microcontroller timing code FSMC bus communication is verified on ALTERA FPGA.
image-scaling--based-on-the-verilog
- 压缩文件中包含丰富的图像缩放算法，都通过Verilog语言编写的，并包含相应的pdf文件。-Compressed file contains rich image scaling algorithm, written by Verilog language, and contains the corresponding PDF files.
costas_DPSK
- 采用costas环进行DPSK解调的程序。输入数据速率2.4Kbps，载波频率12KHz，采样率1.6MHz， 输入数据位宽12位，快捕带为799.617Hz-Costas ring using DPSK demodulation process. Input data rate 2.4Kbps, carrier frequency 12KHz, sampling rate 1.6MHz, the input data 12 bits wide, fast catching band is 79
gwnseq
- verilog产生高斯白噪声，gwn_en信号产生使能，gdata是幅度服从高斯分布，功率谱密度为定值的高斯白噪声序列，共10位（现实中只能够做到带限，跟dac输出带宽有关，我的系统只能做到300kHz）-verilog Gaussian white noise, gwn_en signal enabled, gdata amplitude Gaussian distribution, power spectral density of white Gaussian noise sequence
i2c-master
- I2C Master Code in Verilog using Finite State Machine.
fuyong
- 四路四bit时分复用复接器设计，完成拨码开关式输入的复接器。-Four-four time division multiplexing bit multiplexer designed to complete the DIP switch inputs of the multiplexer.
ALU_finished
- 8bit四级流水ALU 其中有乘法器除法器加法器减法器开方 移位逻辑运算等等通过顶层来控制选择输出需要的运算值-8bit four water which has a multiplier divider ALU adder subtracter prescribing controlled shift logic operations so operators need to select the output value by the top
mdio_mdc
- mdio verilog 实现-mdio verilog coding
Vendor
- 用verilog编写的自动售货机，基于Basys2平台，共有3种物品可以选，分别为4元，2.5元，1元，可以投入3种类型的货币，分别为1元，5元，10元，共有5个状态。-This is a vending machine which is written by verilog on Basys2 board.
FPGA_CRC
- 用Quartus II 13.0 (32-bit)实现并行计算8位数据宽度的CRC16-CCITT循环冗余码，verilog HDL源代码，并有本人手工计算的原理。本程序已经过ModelSim-Altera模拟，仿真波形文件都在本文件内。-Calculated using the Quartus II 13.0 (32-bit) parallel 8-bit data width CRC16-CCITT cyclic redundancy code, verilog HDL source cod
A_PUF_Design
- 基于fpga的物理不可克隆函数（PUF）模块的实现-A PUF Design for Secure FPGA-Based Embedded Systems